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Conference at a Glance

SNUG Singapore | August 16, 2013

Friday, August 16, 2013

 Time

Description 

8:00-8:50 Registration - Olivia Ballroom Level 4
8:50-9:00 Welcome to SNUG Singapore
9:00-9:45 Keynote Address:
An Engineer Experience Moving from a MNC to a Technology Start-Up
Dr. TAN Guan Hong , Programme Director Institute for Infocomm Research, I2R
9:45-9:55 SNUG Technical Committee Introduction
9:55-10:15 Tea Break - Stamford Foyer Level 4
 

Design Implementation - Track I
Olivia Ballroom Level 4

Design Implementation - Track II
Sophia Ballroom Level 4

Verification & AMS Custom Design
VIP B Ballroom

Tutorial & Breakout Session
Canning Ballroom Level 4

10:15-10:45

Timing Sign-Off Methodology in 20nm Technology: Process and Design Perspective

An Overview of Quad-Core A7 CPU Implementation

A Realistic Approach To Account LDE Effect In Timing Library Characterization

Tutorial: AMS Designs in Advance Node

10:45-11:15

Cone Extraction Technique for Incremental Static Timing Analysis

Sign-Off Accuracy Hierarchical Design Interface Timing Budgeting Flow in SoC Design

Automating SoC Based UVM Verification Environments

Tutorial: Accelerate Functional ECO Implementation with Formality Ultra

11:15-11:45

Design and Implementation of Custom On-Chip Clock Controller

Assistive Split Load Utility for High Fanout Clock Maximum Transition Violations

Analog Mixed-Signal Simulation in VCS

Tutorial: Quick FPGA Prototying Platform Bring-up and Design Debug

11:45-12:15

Design Explorer - The "Little" Design Compiler That Punches Above its Weight

DFM Driven Scan Failure Analysis Using Synopsys Yield Explorer

Python Based Layout Automation Practice with PyCell Studio

12:15-1:15 Lunch - Canning Ballroom Level 4
1:15-2:15

Technology Keynote: - Olivia Ballroom Level 4
Advanced Design, Regardless of Process Technology Node
Mr. Don Chan, Vice President, Research and Development, Synopsys Inc.

2:15-2:45

Better ICC to PrimeTime Correlation with Pseudo AOCV Table

Parallel ECO Work Model

Abstract PCell Schematic


2:45-3:15

A Novel Approach of FPGA-Based ATPG Scan Compression

Optimum Design Planning with DC-Graphical and ICC-DP

Tutorial: UVM Best Practices


3:15-3:30 Tea Break - Stamford Foyer Level 4
3:30-4:15

Tutorial: Galaxy-ECO: The Fastest and Most Effective Solution for DRC, Timing and Leakage Power Closure

Tutorial: Easing Floorplanning with Data Flow Analyzer

Tutorial: An Integrated Approach to Designing the Right SoC Architecture, Starting Software Development and SoC Validation Earlier Using Prototyping

 
4:15-5:00

Tutorial: Pre-route Layer Optimization and Correlation To Post Route


5:00-5:15 Best Paper Awards & Lucky Draw! - Olivia Ballroom Level 4