| 10:30-12:00 |
TA01 - FinFET Panel
FinFET Technology and Early Experiences
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TA04
TA04-A Transaction Based Assertion for Transaction Level Coverage, Property and Protocol Checking
TA04-B Sub-cycle Functional Timing Verification using SystemVerilog Assertions
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TA05 - Synopsys Discovery VIP
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TA06 - Maximizing Signoff Productivity
PrimeTime HyperScale - Hierarchical STA
Simultaneous Multi-Voltage Analysis for Faster Timing Signoff
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TA07 - Network Software Development using Virtual Prototypes
Ease Debug and Control of Network Software Using Virtual Prototypes to Do Full System Simulation
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TA08 - Verification using Verilog-AMS
Analog and Mixed-signal Verification Methodology Using Verilog-AMS
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TA09 - Implementing 10G Backplane Systems
Achieving Predictable and Highly Reliable 10G Backplane Designs
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| 1:30-3:30 |
TB01 - Implementation Flows for ARM Cortex-A7 and Cortex-A15 Cores
Power-Centric Timing Optimization of an ARM® Quad Core Cortex™-A7 Processor
Engineering Trade-Offs in the Implementation of a High Performance Dual Core ARM® Cortex™-A15 Processor
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TB02 - Physical Verification of a Production FinFET SoC with IC Validator
Advancements in Density Management at 20nm and below with IC Validator
FinFET Physical Verification of Production Designs with IC Validator
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TB03 - Meeting Test Quality Goals
Meeting Quality Goals for Gigascale Designs: Trends and Solutions
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TB04
TB04-A Challenges with Design and Verification of State Retention in a Complex Low-Power SoC
TB4-B Formal Verification of Floating-Point Arithmetic Datapath Block
TB04-C A Reusable Verification Testbench Architecture Supporting C and UVM Mixed Tests
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TB05 - Integrating Virtual Platforms into Hardware Accelerated RTL
Introduction to Integration of Virtual Platform Technologies with Hardware Accelerated RTL
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TB06 - Leakage Recovery with PrimeTime
Signoff Driven Timing Closure with PrimeTime: Now Includes Leakage Reduction
Leakage Recovery across Multiple Timing Scenarios
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TB07 - SoC Architecture Optimization
Low Power Video Processing for the Mobile SoC: How Analysis of HW-SW Partitioning Gets the Most from Embedded GPUs
SoC Architecture Analysis and Optimization Using Synopsys Platform Architect MCO
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TB08
TB08-A A Practical Look at Current Analysis in FastSpice
TB08-B Transistor Level Static Circuit Analysis to Tackle ERC & ESD Challenges
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TB09
TB09-A Deriving Timing Budgets for DDR4 Interfaces
TB09-B In the Cloud with PCI Express IP
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TB10 - Synopsys Discovery VIP Workshop
Accelerating SoC Verification Using Discovery AXI™ VIP and AXI Interconnect Model
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| 3:45-5:15 |
TC01
TC01-A Advanced Retention Power Gating: Unlocking Opportunistic Leakage Savings in High Performance Mobile SoCs - Technical Committee Award, Honorable Mention 
TC01-B Panel - Achieving Optimum Results on High Performance Processor Cores
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TC02 - Design Environments using Lynx
Using the Lynx Design System to Lower the Cost of Bringing up a New Flow on a New Node
Standardized Design Environment and Methodologies Enable Simultaneous Implementation of 28nm Designs on a Single Flow
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TC03 - Small Delay Defect Model and Advanced Debugging Test
Improving At-Speed Test Quality with the Small Delay Defect Model
Advanced TetraMAX Debugging Techniques for AMD's High-Performance Cores
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TC04 - Transaction-level Verification with ZeBu-Server
Transaction-level Verification with ZeBu-Server - What, When, How
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TC05 - Low Power Verification Debug
Can You Tell Your ISO from LS? - A Methodology for Low Power Debug
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TC06 - Mode-Merging using PrimeTime
Using Mode-Merging to Reduce Scenarios Required for Timing Closure and Signoff
Automated Mode Merging of Timing Constraints using PrimeTime
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TC07 - Power Management Software Development using Virtual Prototypes
Using Virtual Prototypes for the Early Bring-Up and Test of Power Management Software
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TC09 - Increasing ARC Performance and Reducing Power
Increasing Performance and Reducing Power through Memory Request Optimization
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TC10 - Synopsys Discovery VIP Workshop
Accelerating SoC Verification Using Discovery AXI™ VIP and AXI Interconnect Model
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