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Conference at a Glance

SNUG Israel | June 18, 2013

Tuesday, June 18, 2013

 Time

Description 

8:30-9:00 Registration and Breakfast
9:00-9:15 Welcome:
Zachi Feldman, Broadcom, SNUG Israel User Chair
9:15-10:45 Keynote: Accelerating Innovation in the Era of Exponentials - John Chilton - Senior Vice President, Marketing & Strategic Development, Synopsys

Industry Keynote: 60GHz - a Journey Through the Present and Future Wireless Giga-bps Connectivity - Yaron Elboim - Vice President of Engineering, Wilocity
10:45-11:15 Break
 

Verification A - B

Implementation A - B

AMS and Test

IP

11:15-12:40

A1 - Vision Session - Verification

Verification Continum

A3 - From FinFETs to ECOs

Design with FinFET & Double-Patterning, a Brief History of the Future

New Technologies for Faster Implementation of Functional ECOs

A5 - Custom Design - Overview and User Experience

Laker 3 Custom Layout System - "An Advanced Process Node Custom Layout Tutorial"

A6 - ARC Tutorial and User Experience:

Efficient High-Performance Processing

12:40-1:30 Networking Lunch
 

Verification A

Verification B

Implementation A

Implementation B

AMS and Test

IP

1:30-3:00

B1 - Tutorial and User Experience: Designing and Debugging with Verdi3

Verdi3 Transaction-based Debugging for SoC Designs

A New Automated Gate-Level Waveform from RTL Waveform Generation Methodology - Reduces Power Estimation Time from Weeks to Hours

B2 - Tutorial and User Experience: Emulation and Congruency

Transaction-level Verification with ZeBu-Server - What, When, How

Hardware Congruency - Introducing Hardware Semantics for RTL Simulations

B3 - Tutorial: Static Timing Analysis - Signoff

PrimeTime - New, Faster Timing Closure Technologies

B4 - User & Tutorial Session: Hierarchical Design, Multi-source Clock, ICC-2013.03 Update

Feed Through Insertion at Hierarchical Design Flow

High-Speed Clock Tree Implementation Using "Multi Source CTS" Capabilities

ICC 2013.03 Release Update

B5 - Tutorial: Advancing AMS Verification

Advanced AMS Verification and Techniques using Synopsys FastSPICE and Mixed-Signal Solutions

B6 - Tutorial: Implementing 10G Backplane Systems

Achieving Predictable and Highly-Reliable 10G Backplane Designs

3:00-3:20 Break
3:20-4:50

C1 - User Experience: Verification Efficiency, Use of Pre-compiled IPs, System Verilog Interfaces

Tuning VCS Compilation with Pre-compile IP Flow

Reducing Gate-Level Cycle Time Using VCS Advanced Features

System Verilog (SV) Interfaces for RTL-Design

C2 - Prototyping Tutorial

Synthesis Methods for FPGA-based Prototyping and HAPS-70 Family Overview

C3 - Low-Power Experience and DC Updates

Implementing UPF Flow for SoC Design at Intel

Introduction of Multi-Bit Banking Solution

DC 2013.03 Release Update

C4 - Tutorial: Implementation Flows for ARM Cores

Engineering Trade-Offs in the Implementation of a High-Performance Dual Core ARM® Cortex™-A15 Processor

C5 - Tutorial and User Experience: Design for Test

Use of Synopsys Inserted Scan Wrappers in SoC ATPG

Meeting Test Quality Goals in Hierarchical Designs

C6 - Tutorials: Hardening DSP Cores and PCI Express IP

Hardening DSP Cores for Performance with DesignWare Logic Libraries and Embedded Memories

In the Cloud With PCI Express

4:50-5:00 Best Paper Award and Prize Drawing