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Conference at a Glance

India | June 12 - 13, 2013

Wednesday, June 12, 2013
Thursday, June 13, 2013

Wednesday, June 12, 2013

 Time

Description 

7:30 Registration and Breakfast
9:00 Welcome: Arindam Ghosh, Sr. Technical Manager, Global Technical Services, Synopsys

Keynote Address: Massive Innovation and Collaboration into the "GigaScale" Age!
Aart de Geus, Chairman and co-CEO, Synopsys
10:15 Break
 

IC Verification

IC Design: Signoff

Custom Design and AMS Verification

IC Design: Test and FPGA

10:30

WA1: Synopsys User and Tutorial Sessions

WA1.1 Tutorial: Zebu Overview, Easier HDL Cosim, Productivity Techniques

WA1.2 User Paper: Zebu Transactors for Verification & Validation

WA1.3 User Paper: Methodology and Recommendations to Minimize Silicon Bugs with Netlist Simulation

WB1: Synopsys User and Tutorial Sessions

WB1.1 User Paper: Addressing Signoff Timing Quality and Cycle Time Challenges in High Performance Processor Designs

WB1.2 User Paper: Novel Approach to do Multi Voltage Signoff using SMVA

WB 1.3 Tutorial: PrimeTime - Key Technologies and Updates

WC1: Synopsys User and Tutorial Sessions

WC1.1 Tutorial: Laker Custom Layout System - "An Advanced Process Node Custom Layout Tutorial"

WC1.2 User Paper: FineSim for Complex Mixed-Signal SoC Verification

WC1.3 User Paper: Custom Routing Flow Enablement for Advanced Nodes

WD1: Synopsys User and Tutorial Sessions

WD1.1 User Paper: Increase ATPG Throughput While Reducing Care Bits: Optimizing Transition Fault Patterns

WD1.2 User Paper: Effective ATPG with Hierarchical DFT Methodology for SoC

WD1.3 User Paper: Sharing Scan-Ins For Similar Cores

WD1.4: New, Innovative Test Technology to Reduce the Cost of Quality

12:15 Lunch
12:30 Lunch
1:15

WA2: Synopsys User Session

WA2.1 User Paper: X-Propagation - Improving the Methodology in Uncovering X-optimism Issues

WA2.2 User Paper: Certitude for Functional Safety

WA2.3 User Paper: Reconfigurable Verification Environments with Discovery VIP & Reusable Test Cases Using SystemVerilog DPI

1:30

WB2: Synopsys User Session

WB2.1 User Paper: Handling Non-monotonic Delays in Static Timing Analysis

WB2.2: TAT Improvement in Signoff Extraction using SMC Flows

WB2.3 Tutorial: Handling of Advanced Technology and Process Challenges in Parasitic Extraction using StarRC

WC2: Synopsys User Session

WC2.1 User Paper: Determining PLL Clock Jitter Characteristics Using XA-VCS Mixed-Signal Simulations

WC2.2 User Paper: Dynamic Electrical Rule Checking (ERC) Capability in FineSim to Avoid Hot-Spots & Achieve Low-Power Specification

WC2.3 User Paper: EMI & SSO simulation on board: Modelling, Analysis, And Design Solutions

WD2: Synopsys User & Tutorial Session

WD2.1 Tutorial: The Essentials for an Integrated Synplify-Vivado Design Flow Targeting Xilinx 7 Series FPGAs

WD2.2 User Paper: A Methodology of Automation of SoC Validation using FPGA

2:45 Break      
3:00 Break
3:00

WA3: Synopsys User Session

WA3.1 User Paper: AFE Verification - A Novel approach for Mixed Signal Verification

WA3.2 User Paper: Generic RAL Infrastructure to Address Register Verification Challenges

3:15

WB3: Synopsys User and Tutorial Session

WB3.1 User Paper: The Last Microwatt - Challenges in Pre Silicon Power Estimation for Low-Power SoCs

WB3.2 User Paper: Method for Collapsing Multiple Modes Timing Constraints

WB3.3 Tutorial: Mode Merging using PrimeTime-GCA

WC3: Synopsys User and Tutorial Session

WC3.1 User: On Chip Adaptive Voltage Scaling to Minimize Dynamic Current Consumption

WC3.2 Tutorial: Characterizing Memories and Black Boxes: Belling the Cat

WD3: User and Tutorial Session

WD3.1 User Paper: Simplify Secure System Validation and Development: HAPS Prototyping Case Study

WD3.2 User Paper: Challenges in Mapping Multi-core A15 ARM Processor on FPGA

WD3.3 Tutorial: My BFF FPGA-based Prototyping Solution: Better, Faster and Flexible

5:15 Designer Community Expo
6:00 PrimeTime Special Interest Group (SIG) Dinner Advanced ECO Methodology

 

Thursday, June 13, 2013

 Time

Description 

7:30 Registration and Breakfast
9:00 Welcome: Arindam Ghosh, Sr. Technical Manager, Global Technical Services, Synopsys

Keynote Address: The Role of Intelligent Silicon in Addressing Data Deluge Gap
Raman Santhanakrishnan, Managing Director, LSI India R&D Pvt Ltd
10:15 Break
 

IC Design: Implementation

IC Verification

Systems and IP

IC Design: Low Power

10:30

TA1: Synopsys User and Tutorial Sessions

TA1.1 Tutorial: Design with FinFET & Double-Patterning, a Brief History of the Future

TA1.2 User Paper: Physical Design Challenges of a High-performance FPGA in 22nm Process Technology

TA1.3 User Paper: Floorplanning is an ART and with DFA You are an Artist!!

TB1: Synopsys Tutorial Sessions

TB1.1 Tutorial: Addressing Low Power Verification Challenges with VCS

TB1.2 Tutorial: Transaction Level Verification with Zebu Server

TC1: Synopsys User and Tutorial Sessions

TC1.1 Tutorial: Low Power Video Processing for the Mobile SoC: How Analysis of HW-SW Partitioning Gets the Most from Embedded GPUs

TC1.2 User: Integration of Synopsys DesignWare DDR Controller & DDR3/2 PHY IP in 28nm

TD1: Synopsys User and Tutorial Sessions

TD1.1 User Paper: Dynamic Power Optimization Techniques for Highly Switching Design In Physical Implementation

TD1.2 User Paper: Efficient Methodology for Leakage Optimization with Synopsys Tools

TD1.3 User Paper: Handling Nested Power Domains in Complex SoC

TD1.4 Tutorial: Unlocking the Low Power Potential of your Chip - An Advanced Flow Methodology using UPF2.0

12:30 Lunch
1:30

TA2: Synopsys User Session

TA2.1 User Paper: Optimization Techniques for Designing a Channel Dominated High Activity Multimillion 500+Sq mm Chip

TA2.2 User Paper: In-Design 20nm Physical Verification Closure Within ICC Using ICV

TA2.3 User Paper: Multi-Pronged Approach to Address Nanometer Physical Verification Challenges

TB2: Synopsys Tutorial Session

TB2.1 Tutorial: Advanced Verification Debug Productivity with Verdi3 and Siloti

TC2: Synopsys User Session

TC2.1 Tutorial: Designing IP for FinFET Technology: The Opportunities and Challenges

TC2.2 User Paper: Synopsys Virtual Prototypes for Pre-Silicon Software Development - Texas Instrument's Latest Experience

TD2: Synopsys User & Tutorial Session

TD2.1 User Paper: Novel Low Power Static Checking Methodology now Integrated in MVRC

TD2.2 Tutorial: Next Generation Static Verification Platform (Verdi Signoff) - Low Power

3:00 Break
3:15

TA3: High-Performance Cores

TA3.1 User Paper: Synthesis Techniques for Faster Design Closure of High Performance Quad Core Processor

TA3.2 User: GHz ++ : A Step by Step Tutorial on Recovering That Extra Picosecond

TA3.3 Tutorial: Engineering Trade-Offs in the Implementation of a High-Performance Dual Core ARM® Cortex™-A15 Processor

TB3: Synopsys Tutorial Session

TB3.1 Tutorial: Certitude for Functional Qualification

TB3.2 Tutorial: VCS Technologies for Improved Performance and Productive Analysis

TC3: Synopsys User and Tutorial Session

TC3.1 Tutorial: Ease Debug and Control of Network Software using Virtual Prototypes to do Full System Simulation

TC3.2 User Paper: Virtual Prototype for Infineon MCU Using Synopsys Virtualizer

TD4: High-Performance Cores Session

5:00 Best Paper Awards