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Conference at a Glance

SNUG Germany | May 14, 2013

Tuesday, May 14, 2013

 Time

Description 

8:00-9:00 Registration and Breakfast
9:00-9:45 Welcome and Introduction:
Frank Poppen, OFFIS Research Institute and SNUG Germany Technical Chair

Video Message from Aart de Geus, Chairman and Co-CEO, Synopsys, Inc.

Program Overview: Peter Rothenaicher, Senior Technical Manager, Synopsys Germany
9:45-10:15 Break
 

Track 1

Track 2

Track 3

Track 4

Track 5

Track 6

10:15-11:45

A1 - Front-End Implementation - Advanced Synthesis

Applying Synopsys Physical Guidance (SPG) Methodology to Address Complex 28nm Design Challenges

Formality 2013.03 Update and Hierarchical UPF Flow

A2 - Backend Implementation - Advanced Applications

Achieving Timing Convergence by Resolving Congestion and Improving Clock Skew

Analog Net Routing with IC Compiler Custom Co-Design Flow

Resolving the Double Trouble in 20nm Place and Route

A3 - System Design - Architecture Analysis

Power Modelling of 3D-Stacked Memories with TLM2.0-based Virtual Platforms

High-Level Power Modeling with Synopsys Platform Architect - A Signal Processing Use-Case

Low-Power Video Processing for the Mobile SoC: How Analysis of HW-SW Partitioning Gets the Most from Embedded GPUs

A4 - Analog Mixed-Signal Verification I

Enabling XA for Spectre-based Process Design Kits: a Look at Modeling Qualification

An Accurate Path Verification to Secure and to Speed up Nanometer Design Closure

Circuit Check Extension to Optimize ERC Flow, User Experience and Guidelines for Expert and Novice Users

A5 - Digital Verification

Making the Most of SystemVerilog and UVM:
Hints and Tips for New Users


VCS Technologies for Best Debug and Analysis

A6 - Vision Session - High-Performance Core Implementation

Engineering Trade-Offs in the Implementation of a High-Performance ARM® Cortex™-A15 Dual Core Processor

Design with FinFET

11:45-13:15 Networking Lunch
13:15-14:45

B1 - Implementation - Low Power

Improved Methodology for Leakage Optimization in Synopsys Tools

Low-Power Verification using Power State Table Coverage

Meeting Quality Goals for Gigascale Designs Trends and Solutions Part 1

B2 - Implementation - Signoff

Double Patterning. Something to Worry about in Parasitic Extraction?

Static Noise Analysis Including Power Noise

Qualification of Setup/Hold Time Calculation in PT 2012.06 without Delta Transition

B3 - System Design - Virtual Prototyping

Introduction to Hybrid Protoyping

Next-Generation Prototyping - a Hybrid Approach

Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures

B4 - Analog Mixed-Signal Verification II

The Art of Reliability: Guidelines to Reduce IR-drop and Electro-migration Effects in Full Custom Designs

Transistor Level Static Circuit Analysis to Tackle ERC & ESD Challenges

Analog and Mixed-signal Verification Methodology Using Verilog-AMS

B5 - New Technology - Verification Springsoft

Introduction to Verdi3 Automated Debug System

Certitude and VCS at Module-level: a User's Experience

Get Certitude About Your Tapeout Quality

B6 - Vision Session: High-end Implementation Trends

Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor

Emerging Node Challenges and Opportunities

14:45-15:15 Break
15:15-16:45

C1 - Implementation - Test

DFT and ATPG for Mixed 2-phase Latch and Edge Triggered Flop-based Designs

Meeting Quality Goals for Gigascale Designs: Trends and Solutions

C2 - Implementation - Advanced ICC Features and Methodologies

Clockgating and Concurrent Clock & Data Optimization in IC Compiler for Improved Timing Closure

C3 - System Design - Prototyping & HLS

Model-based Design with Synphony MC High-Level Synthesis

C4 - Full Custom Design

Moving from Virtuoso to Synopsys Custom Designer

Laker Custom Layout Solution: An Advanced Process Node Custom Layout Tutorial

C5 - IP - Implementation & Verification

High-Speed Interface IP Selection, Module Level, and Chip Top Level Verification

FPGA-based Emulation of an Ultra Low-Power SoC

Comprehensive System Validation of an Ultra-Low Power SoC with an FPGA-based Emulation System

C6 - Design Flow - Lynx Design System

Using the Lynx Design System to Minimize the SoC Implementation Effort and Cost

Improve Design Quality with Efficient Design Exploration in Lynx Design System

16:45-18:30 Awards and Refreshments