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Conference at a Glance

SNUG Canada | October 1, 2013

Tuesday, October 1, 2013

 Time

Description 

7:30-9:00 Registration and Breakfast
9:00-10:30 Welcome: Costas Conistis, Synopsys, Inc.

Keynote Address: Accelerating Innovation in the Era of Electronics That Increasingly Impact Everyone, Everything, Everywhere
Chi-Foon Chan, President and co-CEO - Synopsys, Inc.

10:30-10:45 Break
 

Verification

Back-End Implementation

Front-End Implementation

10:45-12:15

A1 User Session: Performance and Regression Management

SoC Simulation Performance - Take a Second Look at Your VCS Setup

FPGA Continuous Integration with Jenkins

A2 Tutorial Session: Using Concurrent Clock and Data Optimization for Improved Timing Closure

Achieving Higher Frequencies for Your Design with Early Clockgating Optimization and Comprehensive Useful Skew

A3 User Tutorial Session: Lynx and Signoff Driven Timing Closure

I Love Lynx

Signoff Driven Timing Closure with PrimeTime: Now Includes Leakage Reduction


12:15-1:15 Lunch
 

Verification

Back-End Implementation

Front-End Implementation

1:15-2:45

B1 User Session: Reuse & Low Power Verification

Test Driven Design: Unit Testing... on Steroids

UVM-Based Vertical DV Re-use in Packet Processing ASICs

Verifying Crossover Signals in Low Power Simulation

B2 User & Tutorial Session: MultiSource CTS and Design Closure

The Clear Advantages of Multi-Source CTS Technical Awared Winner

20nm Design Closure in IC Compiler Using IC Validator in-Design

B3 User Paper & Tutorial Session: Test Using IEEE 1500 and PrimeTime Multi-scenario Technology

Design Reuse and Pin Limited Test Using IEEE 1500

PrimeTime Multi-scenario Technology
2:45-3:00 Break
 

Verification

Back-End Implementation

Front-End Implementation

3:00-4:30

C1 Tutorial Session: UVM Verification IP Reuse and Debug

Leveraging UVM and Discovery VIP for Better and Faster Verification

C2 Tutorial Session: IC Compiler ECO Flow For Minimum Physical Impact (MPI)

IC Compiler ECO Flows for Minimal Physical Impact

C3 User & Tutorial Session: Power Aware ATPG and Formality ECO

Power Aware Automatic Test Pattern Generation for ASIC Using TetraMAX

Speeding ECO Implementation and Verification with Formality Ultra


4:30-6:00 SNUG Pub and Awards Presentation