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Conference at a Glance

SNUG Boston | September 12, 2013

Thursday, September 12, 2013

 Time

Description 

8:30-9:15 Registration and Breakfast
9:15-10:30 Welcome: Jay Wasserman, SNUG Boston Technical Chair - Analog Devices, Inc.

Keynote Address: Massive Innovation and Collaboration into the "GigaScale" Age!
Aart de Geus, Chairman and co-CEO, Synopsys, Inc.

10:30-10:45 Break
 

Verification

FPGA Implementation & Prototyping

Frontend Implementation: Formality

Physical Implementation

Test

Full Custom Design and AMS Verification

10:45-12:15

A1 User Paper Session: Advanced Verification Techniques

Managing Verification of Highly Parameterized Designs

Who's Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification Environment

B1 Tutorial Session: Advanced FPGA Implementation

Designing with Xilinx 7 Series FPGAs

Integrating Custom Logic in SoC FPGAs

C1 User Paper & Tutorial Session: Frontend Implementation - Multi-Voltage Design Verification and Formality Ultra

Successful Multi-Voltage Design: Using Power-aware Equivalence Checking and Static MV Analysis to Boost Tape-out Confidence

Winner, Technical Committee Award Technical Committee Award

Advanced Debugging Features of Formality Ultra

D1 User Paper & Tutorial Session: Plug In and Sign Off: Physical Verification Within IC Compiler

Conquering First 20nm Tapeout Challenges with IC Compiler and IC Validator

20nm Design Closure in ICC using IC Validator in-Design

E1 User Paper & Tutorial Session: Advanced Test Techniques

Placement Based Analysis of Scan Test ATPG Results

Meeting Quality Goals for Gigascale Designs: Trends and Solutions (Part 1)

F1 User Paper & Tutorial Session: Transistor-level Static Timing

Accurate Timing of Dynamic Circuits Using NanoTime Static Timing Analysis

Differential Full-swing Static Timing Analysis Enhancements to NanoTime

12:15-1:15 Lunch
 

Verification

FPGA Implementation & Prototyping

Frontend Implementation: Optimization

Physical Implementation

Test

Full Custom Design and AMS Verification

1:15-3:15

A2 User Paper & Tutorial Session: Coverage Closure and Other Verification Topics

Covering the Gap: A Tutorial on Coverage-Driven Verification Methodology

Making the Most of SystemVerilog and UVM: Hints and Tips for New Users

Coverage Closure and Debug Using Symbolic Simulation

B2 Tutorial Session: FPGA Prototyping and Verification

Formal Verification of FPGAs

Verifying Low Power ASIC Design Specification (UPF) via FPGA Prototyping

Using FPGA-based Prototyping Systems for M-PCIe System Development

C2 User Paper & Tutorial Session: Frontend Implementation - Optimization

Applying DOE to Logic Synthesis and Placement

DC Graphical Layer Optimization

What's New in Synthesis from R&D's Perspective

D2 Tutorial & User Paper Session: Taking Your Design Skills to the Next Level

Multisource CTS: Achieve Higher Frequencies for Your Design

Application of the Multisource CTS Operative in IC Compiler

Engineering Trade-Offs in the Implementation of a High-Performance Dual-core ARM® Cortex™-A15 Processor

Employing Data Flow Analysis Techniques

E2 Tutorial Session: Improving Test

Meeting Quality Goals for Gigascale Designs: Trends and Solutions (Part 2)

Debugging Low Test Coverage

F2 User Paper & Tutorial Session: Custom Design and Layout

Corner Wiring and Via Placement Made Easy in Custom Designer Layout Editor

Laker3 Custom Layout System - "An Advanced Process Node Layout Tutorial"

 

Verification

FPGA Implementation & Prototyping

Frontend Implementation:
Test & Low Power

Physical Implementation

Static Timing

Full Custom Design and AMS Verification

3:30-5:00

A3 User Paper Session: UVM Based Verification Techniques

Considerations for Development and Support of Exportable UVM IP

Getting Around the UVM "One Test-top Approach"

B3 Tutorial Session: System Implementation and Verification

Application-Specific Processor Design and Prototyping

Complex SoC Prototyping Using Xilinx Virtex-7-Based HAPS-70 Systems

C3 Tutorial Session: Frontend Implementation: Test & Low Power

Test it, Test it, You Want to Test it!

How Low Power Can You Go?

D3 Place and Route Vision Session

Advances in Place and Route Technology

E3 User Paper & Tutorial Session: Static Timing

Timing Verification for CDC Paths in Large-scale SoCs

PrimeTime Advance Topics and Flows

F3 Tutorial Session: FinFET Transistor-level Extraction and Simulation

StarRC Transistor-level Extraction: Optimizing Accuracy and Performance for Custom AMS Flows and sub-20nm Technologies

BSIM-CMG FinFET Model Complexity and its Impact on Synopsys AMS Simulation

5:00-7:00 Awards and Designer Community Expo