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Conference at a Glance

SNUG Austin | September 18, 2013

Wednesday, September 18, 2013

 Time

Description 

8:00-9:00 Registration and Breakfast
9:00-10:15 Welcome: John Dickol, SNUG Austin Technical Chair - Samsung

Keynote Address:
Massive Innovation and Collaboration into the "GigaScale" Age!
Aart de Geus, Chairman and co-CEO, Synopsys, Inc.

 

Front-end Implementation

Physical Implementation

Digital Verification

Analog Mixed-Signal

10:15-10:30 Break
10:30-12:30

FA1 User & Tutorial Session: Advanced PT and 2013.03 Galaxy Update

Using PrimeTime's New Signoff-Driven Leakage Recovery Feature SNUG 2nd Best Paper

Galaxy RTL: Design Compiler Family 2013.03 Update

Methods for Timing Source Synchronous Interfaces and Skew Sensitive Buses

FA2 User & Tutorial Session: ECO Solutions and Tool Correlation for Design Closure

How We Saved Over a Half Million Dollars in Mask Costs Using the Power of IC Compiler's Z-route

IC Compiler ECO Flows for Minimal Physical Impact

Calibrating IC Compiler, StarRC, and PrimeTime for Parasitic and Timing Correlation

FA3 User & Tutorial Session: X-Propagation, Static LP Checking and Random Stability

A Practical Approach to Implementing Synopsys X-Prop Technology on a Complex SoC

Next-Generation Low-Power Static Checking with Verdi Signoff-LP

Random Stability in SystemVerilog

FA4 User Session: FinFET's Impact on the AMS Flow; NanoTime

Planar MOSFET to FinFET: A User Experience With HSPICE, FineSim, StarRC, RAPID3D, RC3

Static Timing Analysis Pessimism Reduction through Clock Shaping

Accurate Transistor-level STA Methodology for 20nm Custom SRAM Macro Using NanoTime SNUG 3rd Best Paper

12:30-1:30 Lunch
 

Front-end Implementation

Physical Implementation

Digital Verification

Test

1:30-3:00

FB1 User & Tutorial Session: DC-Graphical and UPF

High-Speed and Complex IP Design Exploration Utilizing Recent QoR Improvement Features in Design Compiler Graphical and IC Compiler

Visualization and Debug of UPF with Design Vision GUI

FB2 User & Tutorial Session: FinFET, Emerging Node and High-Speed Clock Mesh Solutions

IC Compiler-based Holistic Clock Methodology

Emerging Node Challenges and Opportunities

FB3 User & Tutorial Session: Verification Quality, Low Power, and Verification IP

Functional Signoff: A Process for Measuring and Improving Verification Quality to Ensure Bug-Free Designs

Challenges and Implications of Verifying Low-Power Features in a Complex SoC

FB4 User Session: ATPG and Defect Diagnosis

Placement-Based Analysis of Scan Test ATPG Switching Activity

In Situ Defect Diagnosis using IEEE 1149.1 and P1687

3:00-3:15 Break
3:15-5:15

FC1 User & Tutorial Session: Structured Placement, Constraints, and Formality

A Fine-Grained Hybrid Approach to Structured Placement and Synthesis

Speeding ECO Implementation and Verification with Formality Ultra

Diagnosis of Vulnerable Constraints Using PrimeTime GCA for Hierarchical Design

FC2 User & Tutorial Session: Advanced CTS Methodology, Crossbar Implementation and 14nm Challenges

Optimizing 1024x1024 Cross Bar Design Employing Relative Placement, Pre-routes and Buffer Pre-placement Flow

IC Compiler Advanced CTS Features and Methodologies

Intro to FinFET: Challenges for 14nm and Beyond

FC3 User & Tutorial Session: UVM and Advanced SoC Debug

Practical Applications with UVM Sequences - Body Building 201

Considerations for Development and Support of Exportable UVM IP

Debug for Advanced SoC Verification and Verdi Road Map

FC4 User & Tutorial Session: Recommended DFT Methodologies

ATPG for Multi-Fault Model, Multi-Testmode, Multi-Frequency, Pin Limited Deep Submicron Devices using On Chip Clock Control

DFT Architecture and Implementation of a Quad-core ARMReg; Cortex™ Processor Targeted for Low-Power, High Performance Applications SNUG 2nd Best Paper

Meeting Quality Goals for Gigascale Designs: Trends and Solutions

5:00-7:00 Awards and Designer Community Expo