Through-Silicon-Via Based 3D IC Research Activities at the
Georgia Tech Computer-Aided Design Laboratory

This talk provides an overview of various 3D IC research projects being conducted at the Georgia Tech Computer-Aided Design (GTCAD) Laboratory. With the support of the US National Security Agency (NSA), we are currently building a many-core 3D processor with stacked memory (arguably the first in academia). Our 3D processor features 64 cores and SRAM memory banks that are interconnected with high-density through-silicon-vias (TSV). Next, we are working on TSV-related design-for-manufacturability (DFM) issues, where the goal is to model the impact of stress, density, and reliability problems caused by TSVs in 3D layouts and provide CAD solutions to mitigate them. Our project funded by the Interconnect Focus Center (IFC) is to investigate efficient design methodologies for micro-fluidic channel-based liquid cooling system for 3D ICs. We are also performing studies on the power delivery and cooling system design challenges for the future many-tier 3D system. Our collaboration with the Center for Circuit and System Solutions (C2S2) deals with the circuit and microarchitectural level co-optimization of 3D designs. Our project funded by the National Science Foundation (NFS) investigates 3D integration of sub-threshold many-core processors and super threshold multi-core processor for highly parallel, ultra low-power co-processing.
Sung Kyu Lim, Georgia Institute of Technology