|EUV OPC flow optimization for volume manufacturing|
This article will investigate EUV-specific issues and solution options for a production mask synthesis flow, including different correction and flow automation approaches. Improved methods help enable EUV optical proximity correction (OPC) tapeout flows to achieve comparable or better metrics than existing 193nm lithography flows.
Sep 09, 2011
|Faster Yield Ramp at Sub-100-nm Technologies Using Design-Centric Volume Diagnostics Approach|
At process nodes below 100 nanometers (nm), achieving yield ramp becomes both more critical and a greater challenge for semiconductor manufacturers. New manufacturing steps, materials and device types, coupled with escalating process variations and a host of other challenges, continually increase the difficulty in device scaling.
Oct 27, 2010
|Accurate EUV lithography simulation enabled by calibrated physical resist models|
This article assess the readiness of rigorous physical resist model calibration for accurate EUV lithography (EUVL) simulation -- first, summarizing the experimental setup for the EUVL and discussing pattern selection for calibration, then illustrating the speed and robustness of model building, which allows overnight determination of accurate models.
Sep 13, 2010
|Yield Metrology Looking at Systematic Failure|
Sagar Kekare of Synopsys discusses his paper on rapid root cause analysis and process change validation using design-centric volume diagnostics in a video interview with Debra Vogler of Solid State Technology.
Jul 14, 2010
|EDN: Design-centric yield management|
In the race to the market, IC vendors have few avenues remaining to claim the first-to-market advantage.
Mar 12, 2009
|EDN: Synopsys tries to organize its efforts in EDA multiprocessing |
It’s hard to imagine a set of applications that need computing resources more than the chain of EDA tools for a 65 nm chip design. (OK, searching for extraterrestrials, maybe, but the economics are a bit different there.)
Mar 10, 2008