In today’s SoCs, the convergence of multiple functions causes very complex interaction between advanced interface protocols and logic. Combined with the growing number of IPs used, the very large design sizes, and complex clocking, is causing the number of paths crossing clock domains to explode. These forces combine and create the demand to find all CDC issues as early as possible in the design cycle, to avoid tedious debugging late in verification stages, or far worse, missing a CDC bug, resulting in expensive silicon re-spins, or even more expensive field returns. Synopsys’s VC CDC solution provides comprehensive CDC verification for SoCs at full-chip RTL, enabling designers to find and debug CDC issues early in the design cycle.
VC CDC Datasheet
Static Clock Domain Crossing (CDC) Checking Challenges
CDC verification for huge SoC designs at the flat full-chip level is extraordinarily challenging. In the past, this has forced users to adopt hierarchical or block-based methodologies, which risk missing inter-block design-level CDC bugs.
Setting up a design from scratch for CDC verification has been a daunting task, requiring significant effort to ensure consistency with implementation flows. Silicon bugs can escape if CDC verification setup is inconsistent with implementation setup.
Design styles and methodologies vary between design groups, resulting in different CDC verification needs. If CDC verification is not tuned for each design style, excessive violation reporting noise may result. Previously, users manually waive violations, which is tedious and error-prone—potentially resulting in bug escapes.
Low power implementation infers and synthesizes additional logic, which can introduce CDC bugs. CDC verification must accurately match LP power logic inference and catch such problems upfront at RTL.
With complex designs, debugging CDC bugs can be very tedious and affect designer productivity. Designers are looking for solutions which can easily and quickly pinpoint the root cause of CDC problems.
Figure 1: Clock domain coloring and locators
Key Features and Benefits
- Synopsys Design Constraints- Based Setup
Static CDC verification requires key parameters such as the list of clocks, asynchronous clock groups, constants in design (like scan mode), boundary (input/ output) port clock relationships and the like to be accurately specified. VC CDC will extract automatically all the information from the Synopsys Design Constraints (SDC) file, making setup of CDC verification easy and accurate.
- Reuse Design Compiler Synthesis Setup
Original Design Compiler® scripts can be reused for VC CDC design read and design query, enabling minimal learning curve needed for performing advanced static CDC verification.
- Comprehensive Synchronizer Detection
VC CDC automatically recognizes and identifies all synchronizer types and variants used in today’s designs, such as multi flip-flop, data mux, logic based, clock gating, handshake, FIFO, etc. (See Figure 2).
Figure 2: Variations in N-FF synchronizer
- Adaptive Synchronizer Detection Based on Design Style
VC CDC provides the highest CDC checking accuracy, with the fewest type I errors (false detects) and zero type II errors (false accepts). Eliminating false accepts and false detects as part of CDC verification can be controlled via a Synopsysunique synchronizer detection configuration methodology based on design style and methodology.
- Performance & Capacity to Check SoCs at Full- Chip RTL Flat
VC CDC provides at least 3X performance and capacity advantage over any other capability, and can load and check enormous SoCs at full chip RTL flat. This enables VC CDC to catch chip-killing bugs that will be missed by any hierarchical CDC tool or methodology (See Figure 3).
Figure 3: SoC-level block-to-block reconvergence
- Root-Cause Analysis with Visual Debug
VC CDC guides users by pinpointing the root cause in the schematic for every violation. This provides context specific guidance and helps user to fix the problem quickly (See Figure 1).
- Power-Aware CDC Checks
Low power implementation can create new CDC paths post synthesis. Power-aware CDC checks predicts these issues accurately by leveraging VC LP’s next-generation low power static checking engine, providing excellent alignment and correlation with Synopsys Low Power flows.
- Comprehensive Reset Verification
VC CDC provides complete reset verification, covering checking for synchronous de-assertion of reset, cascaded synchronizers and reset convergence.
Figure 4: Design Compiler/IC Compiler-like scripting
- Industry-leading performance and capacity
- Ability to efficiently run on the largest SoC designs at RTL
- At least 3X-5X faster and higher capacity than other tools
- Excellent ease of adoption and ease of use
- Use model and commands tightly aligned with Synopsys implementation tools
- Synopsys’ VC CDC scripts look just like Design Compiler TCL scripts (See Figure 4)
- Reporting filtering and waivers
- Highly flexible tag- and messagebased filtering and waiving capabilities for rapid and effective CDC verification signoff flows
- Powerful CDC optimized debug
- GUI-based CDC debugging with clock domain coloring and source code views
- Unique CDC-specific visual guidance, including box-in-box representation and CDC specific locators to pinpoint problems
CDC verification for today’s advanced SoC designs is a daunting task due to huge design sizes and the incredibly complex interactions between very large number of clocks. Synopsys’ VC CDC provides comprehensive, accurate and low-noise CDC checking, and is able to scale with the size and complexity of today’s largest SoCs. VC CDC is in production deployment and adopted at industry-leading customers.
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