Static and Formal Verification 

Next-Generation Static and Formal Verification Solutions 

VC Formal, VC CDC and VC LP combine to enable designers and verification engineers to quickly analyze and check RTL designs very early in the design flow, with no need for complex setup, testbenches or stimulus. This allows many bugs to be found and fixed before simulation, making simulation faster and more effective, and reducing overall cost, time and effort. Synopsys’ new static and formal verification solutions are built on next-generation databases and engines to provide the capacity and performance required to verify the largest, most complex designs. In addition, VC Formal, VC CDC and VC LP all provide unified design read and common look-and-feel with Design Compiler-like TCL support, enabling rapid and easy adoption and excellent ease-of-use and debug.

  • Tools
 

  • VC CDC
  • Next-generation static CDC static checking solutionmore

  • VC LP
  • Advanced Low Power static checking solutionmore

  • HECTOR
  • Next-generation formal block-level consistency checkermore

 
Delivers high-performance checks between independently developed models and exhaustive verification of successive design refinements all without testbenches, assertions or coverage.


 
Comprehensive equivalence checking of large, complex, multi-voltage SoCs, all types of memories, full custom logic and I/Os.



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