Verification Videos 


DAC 2014 Verification Lunch Panel: SoC Leaders Verify with Synopsys

On June 3, 2014, Synopsys hosted a luncheon event at DAC in San Francisco, CA. At this event, Dave DeMaria, VP of marketing and business development at Synopsys highlighted next-generation verification technologies including Verification Compiler, advanced static and formal technology, and the industry’s fastest emulation system ZeBu Server-3, as well as discussions about the latest developments in the verification landscape and advanced technology trends. A panel of industry experts from AMD, Analog Devices, Cisco, Freescale, and Imagination discuss their insights on SoC verification challenges and how they collaborate with Synopsys to address them.
Dave DeMaria, Vice President of Marketing, Verification, Synopsys; Venkataraman Srinivasagam, Technical Leader, Cisco; Todd Honan, Design Verification Manager, Analog Devices; Alex Starr, Fellow & Pre-Silicon Solutions Architect, AMD; Amol Bhinge, Senior SoC Verification Manager, Freescale; Colin McKellar, Senior Director of HW Verification, Imagination



ZeBu Server video

ZeBu® Server-3 offers simulation-like debug capabilities including full signal visibility and deterministic rerun and debug of multi-billion cycle system-level test sequences. Now, using ZeBu integration with the popular Synopsys Verdi3 debug environment, users can quickly analyze waveforms, perform transaction-level debug and access the same powerful debug environment they are familiar with for simulation. ZeBu’s interactive Combinatorial Signal Access (iCSA) technology enables users to begin debug with full visibility using Verdi3 in minutes, rather than the hours typical of traditional emulation waveform generators. ZeBu’s powerful Post Run Debug mode eliminates the constraint of relatively short logic analyzer trace windows, enabling the user to rerun and analyze any scenario deterministically – even scenarios embedded in multi-billion cycle tests – without recompiling the design.
Synopsys Verification team


SNUG 2014 Verification lunch panel - Addressing the Challenges of SoC Verification
SNUG 2014 Verification lunch panel: Addressing the Challenges of SoC Verification

On March 25, 2014, Synopsys hosted a luncheon event at SNUG in Santa Clara, CA. At this event, Michael Sanie, Senior Director, Verification Marketing at Synopsys highlighted next-generation verification technologies including VCS AMS, ZeBu Server-3 and Verification Compiler. Later, Hillel Miller of Freescale shared his view on enabling Emulation for Layerscape Architecture. Then Baosheng Wang of AMD shares his thoughts on the power verification with Synopsys. Last but not least, we have Brian Hunter of Cavium express his thoughts on why one of us is wrong… and I have the Microphone!
Michael Sanie, Senior Director of Verification Marketing Synopsys, Hillel Miller, Pre-silicon Verification & Emulation Manager, Freescale, Baosheng Wang, Senior MTS & Engineering Manager, AMD, Brian Hunter, Senior Consulting Engineer, Cavium



DVCon 2014 Verification Lunch Panel: Industry Leaders Verify with Synopsys

On March 6, 2014, Synopsys hosted a luncheon event at DVCon in San Jose, CA. At this event, Dave DeMaria, VP of marketing and business development at Synopsys highlighted next-generation verification technologies including Verification Compiler and ZeBu Server-3. Later, Amol Bhinge of Freescale shared his view on what's driving SoC complexity and how his team has achieved success by collaborating with Synopsys.
Michael Sanie, Senior Director of Verification Marketing, Synopsys; Dave DeMaria, Vice President of Marketing, Verification, Synopsys; Amol Bhinge, Senior SoC Verification Manager, Freescale



VC Apps Video Series

This series begins with an introduction to VC Apps. Each month we will cover additional topics related to the various examples of applications you can create with VC Apps. These videos includes real live demos on how VC Apps can help with everyday debug challenges, and that it only takes a few minutes to start reaping the benefits of VC Apps. So if you are ready to customize your debug experience, remember that everything you need to get started is just a click away. If you are familiar with Verdi, you already know that Verdi is a powerful and intuitive debug platform used by thousands of engineers across the world. VC Apps allows you to customize your Verdi workflow, directly interact with Verdi’s design and signal data, or link Verdi to other applications. The VC Apps Exchange website offers a variety of documents such as training materials, reference manual, VC Apps example apps and an active forum of experts.
Steve Chappell, Senior Manager, CAE Technology Group, Verification, Synopsys



Verdi3 HW SW Debug Video

This video demonstration shows an overview of the Synopsys Verdi3™ Hardware and Software Debug solution, an instruction-accurate debug solution for SoC designs containing embedded software. Embedded software plays a critical role in driving today's SoC verification. We observed that it has become increasingly difficult to perform traditional hardware debug activities due to the software component present in many of today's SoC verification environments. What's really needed is simultaneous view of both hardware and software languages that will help designers efficiently and effectively advance their debug productivity.
Alex Wakefield, Principal Engineer, Synopsys



DAC 2013 Verification Lunch Panel: SoC Leaders Verify with Synopsys

On June 4, 2013, Synopsys hosted a luncheon event at DAC in Austin, Texas. Industry leaders, such as Altera, ARM, Freescale, Qualcomm and STMicroelectronics shared their views on what's driving SoC complexity and how their teams have achieved success. They also discussed the latest developments in verification.
John Chilton, Senior Vice President of Marketing, Synopsys; Sheela Pillai, Director of Verification, Altera; Paul Martin, Senior Product Manager, ARM; Massimo Calligaro, Senior Verification Specialist, STMicroelectronics; Amol Bhinge, Senior SoC Verification Manager, Freescale; Chinh Tran, Senior Director of Engineering


SNUG 2013 Verification Lunch Panel: Industry Leaders Verify with Synopsys
SNUG 2013 Verification Lunch Panel: Industry Leaders Verify with Synopsys

On March 25, 2013, Synopsys hosted a luncheon event at SNUG Silicon Valley in Santa Clara, CA. Industry leaders, such as Qualcomm and NVIDIA shared their views on what's driving SoC complexity and how their teams have achieved success. They also discussed the latest developments in verification.
Rebecca Lipon, Senior Product Marketing Manager, Synopsys; Janick Bergeron, Synopsys Fellow, Synopsys; Lu Dai, Design Verification Lead, Qualcomm; Peter Nelson, Senior Verification Engineer, NVIDIA



ProtoLink Video

This video demonstration shows an overview of ProtoLink, Synopsys' innovative multi-FPGA debug solution for SoC prototype systems. It provides simulator-like visibility and fast debug turnaround time for both HAPS FPGA-based prototyping solutions and custom FPGA prototype boards. ProtoLink allows you to cut prototype debug time in half, improve verification efficiency for early validation of SoC designs, and maximize ROI with faster and earlier deployment.
Josefina Hobbs, Technical Solutions Architect, Synopsys


DVCon 2013 Verification Lunch Panel: Industry Leaders Verify with Synopsys
DVCon 2013 Verification Lunch Panel: Industry Leaders Verify with Synopsys

On February 28, 2013, Synopsys hosted a luncheon event at DVCon in San Jose, CA. Industry leaders, such as Altera and Infinera shared their views on what's driving SoC complexity and how their teams have achieved success. They also discussed the latest developments in verification.
Michael Sanie, Senior Director of Verification Marketing, Synopsys; Prasad Paranjape, Vice President of Engineering, Infinera; Sheela Pillai, Director of Verification, Altera


Verification Futures Conference 2012 Presentation: Will Everything Start to Look Like a SoC?
Verification Futures Conference 2012 Presentation: Will Everything Start to Look Like a SoC?

November 19th-22nd, 2012, Janick Bergeron, Fellow at Synopsys, presented at the Verification Futures Conference in the UK, France and Germany; sponsored by Synopsys and organized by Test and Verification Solutions, Ltd (TVS). In his presentation, Janick discussed emerging verification methods, and how unparalleled R&D investment at Synopsys and partnership with leading practitioners is driving unique technology breakthroughs to overcome their verification challenges of the near future. This recording was captured live at the UK conference; courtesy of TVS.
Janick Bergeron, Fellow, Synopsys


DAC 2012 Verification Lunch Panel: SoC Leaders Verify with Synopsys
DAC 2012 Verification Lunch Panel: SoC Leaders Verify with Synopsys

On June 5, 2012, Synopsys hosted a luncheon event at DAC in San Francisco, CA. Industry leaders, such as AMD, Broadcom, Cavium, Freescale, Qualcomm and ST-Ericsson shared their views on what's driving SoC complexity and how their teams have achieved success. They also discussed the latest developments in verification
Brian Hunter, Consulting Engineer, Cavium; Fabien Nimsgern, Director of CAD, ST-Ericsson; Hillel Miller, Verification Manager, Freescale; Karl Whiting, Verification Architect, AMD; Noumaan Shah, Principal Engineer, Broadcom; Lu Dai , Design Verification Lead, Qualcomm; John Chilton, Sr. VP of Marketing, Synopsys


Protocol Analyzer Video Demonstration
Protocol Analyzer Video Demonstration

You won't want to miss this video demonstration that shows protocol debug made easy. In this video, you'll see how the Synopsys Protocol Analyzer provides a graphical view of the transfers, transaction, packets and handshaking of a protocol, to simplify and speed-up the debug associated with complex protocol verification
Josefina Hobbs, Technical Solutions Architect, Synopsys


DVCon 2012 Verification Lunch Panel: Industry Leaders Verify with Synopsys
DVCon 2012 Verification Lunch Panel: Industry Leaders Verify with Synopsys

This highly informative session covers the latest verification trends, challenges and solutions. You will hear Synopsys and leading industry experts share their viewpoints on what is driving SoC complexity, introduction to Synopsys’ next-generation Verification IP architecture, and user perspectives on verification IP, UVM, and other topics.
Michael Sanie, Director of Verification Product Marketing, Synopsys; Alex Wakefield, Principal Engineer Synopsys; Brian Hunter Senior Consulting Engineer, Cavium


2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems
2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems

On January 31, 2012, Synopsys hosted an HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about their experiences using HSPICE in some of their most challenging designs.
Tony Todesco, SMTS Design Engineer, AMD; Johann Nittman, Signal Integrity Engineer, Cavium Networks; Liping Li, Sr. Member of the Technical Staff, Altera; Randy Wolff, Manager, Signal Integrity R&D Group, Micron; Scott Wedge, Sr. Staff Engineer, Synopsys



DAC 2011: Verification Lunch Panel: FastForward to Advanced Verification

Industry leaders share insights into their increasingly complex and diverse verification challenges and how the R&D collaboration with Synopsys has yielded key technology addressing these challenges. More details about these breakthrough technologies as well as the obtained results are presented. Watch the video and learn how a panel of industry experts from MediaTek, Renesas, Freescale and Qualcomm were able to FastForward to advanced verification, and gain insights for your next project.
Kelly Larson, Sr. Technical Marketing Manager, Verification, MediaTek; Eiichi Fukita, EDA Platform Development, Renesas; Hillel Miller, SoC Verification and Emulation Manager, Freescale; Guy Levenbroun, Sr Engineer, Qualcomm



DAC 2011: SPICE Up Your Chip: Achieving Fast, Accurate AMS Verification

On June 7, 2011, Synopsys hosted an dinner event at DAC in San Diego, CA. Hear what industry leaders from AMD, Juniper Networks, nVidia, Qualcomm and Xilinx had to say about using HSPICE and CustomSim in some of today’s most challenging designs.
Dirk Robinson, Analog Design Engineer, AMD; Nikhil Jayakumar, Design Engineer, Global Circuits Team, Juniper Networks; Wen-Hung Lo, Senior Mixed-Signal Design Engineer, NVIDIA; Mohamed Abu-Rahma, Staff Engineer, Memory Circuit Design Team, Qualcomm; Min-Fang Ho, CAD Manager, IC CAD, Xilinx



DVCon 2011: Verification Lunch Panel: Industry Leaders Verify with Synopsys

On March 2, Synopsys hosted a special Verification Luncheon at DVCon 2011 in San Jose. Industry experts from Cavium Networks, Atheros, and AMD discussed complex real-world verification challenges and presented insights into best practices that help address them. This video provides a valuable opportunity to learn about new innovations in verification technology that enable improved performance and productivity.
Brian Hunter, Consulting Engineer, Cavium Networks; Michael Smith, Director IC Design, Atheros; Warren Stapleton, Senior Fellow, AMD


HSPICE SIG Video
HSPICE SIG: A Converging Analog World: Silicon, Package and System

On January 31, 2011, Synopsys hosted its first HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about using HSPICE in some of today's most challenging designs.
Synopsys, Inc.


Fall 2010: Modern Verification Challenges
Fall 2010: Modern Verification Challenges

In this short but insightful interview, Warren Stapleton, Senior Fellow at AMD, discusses the unique challenges of modern day verification, including the growing complexity of today’s microprocessors designs and what this means for verification engineers.
Warren Stapleton, Senior Fellow, AMD; Michael Sanie, Director, Functional Verification Marketing, Synopsys



DAC 2010: Industry Leaders Verification Luncheon

On June15, 2010, Synopsys hosted a special Verification Luncheon event at DAC in Anaheim, CA at which industry leaders from around the world discussed their success using the VCS functional verification solution to address a wide range of verification challenges. The proceedings were captured in this insightful video.
Ali Habibi Senior Formal Verification Engineer, NVIDIA; Maruthy Vedam Senior Staff Manager, Digital Design and Verification, Qualcomm; Hillel Miller Verification Methodology Manager, Freescale; Kazunari Horikawa Chief Specialist, Toshiba; Yuval Shay Staff Engineer, Mixed-Signal Verification.



SNUG San Jose 2010: Functional Verification Vision Session

In this session, Synopsys Fellow Janick Bergeron shares his vision on verification for the coming decade. Although many challenges and principals remain the same as they have for the last 20 years, the approaches to address them change due to the economics of IC design and development. By drawing upon past and current trends, future approaches to these verification challenges are highlighted and discussed.
Janick Bergeron, Fellow, Synopsys


Advanced Verification
DVCon 2010: Advanced Verification Techniques Using VMM 1.2

First presented at DVCon 2010, this tutorial focuses on advanced verification techniques based on the latest VMM release. To help verification engineers get maximum benefit from VMM, this tutorial provides application-oriented information on key VMM features that will boost engineers' productivity and encourage re-use throughout a project's life-cycle and across projects.
Doug Smith, Doulos; Jon Michelson, Verification Central LLC; Faisal Haque, Qualcomm; Badri Gopalan, Synopsys; JL Gray, Verilab, Inc.; Ambar Sarkar, Paradigm Works, Inc.


DesignCon 2010: VCS Named DesignVision Award Finalist

Following the announcement that VCS was honored as a finalist in the 2010 DesignVision Awards, Swami Venkat, Sr. Director of Verification Marketing at Synopsys, discusses the latest innovations within Synopsys' industry-leading functional verification solution at Designcon 2010.
Synopsys



DAC 2009: Coping with Modern AMS Challenges

The guest panel of industry experts discussed how they are addressing key verification challenges at 32 nanometers, achieving high-accuracy verification for complex BCD and FPGA applications, and using power management techniques for custom DSP designs.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; Aaron Barker, Staff Engineer, Sun Microsystems; Eugene Chen, CAD Director, Alter; Sandeep Tare, Verification Methodology Engineer, Texas Instruments; Lyes Djama, Smart Power Design Flows Manager; Pierluigi Daglio, AMS Design & Verification Flows Manager, STMicroelectronics



DAC 2009: Solutions for Tough Verification Challenges

Synopsys hosted a special VCS Verification Luncheon event at DAC in San Francisco, CA focused on the VCS functional verification solution. Verification R&D experts from leading companies discussed how they leverage VCS’s multicore performance, transaction-based verification, tight mixed-signal integration, comprehensive low power verification capabilities and proven methodologies to solve today’s toughest verification challenges.
John Chilton, Sr. VP of Marketing & Corporate Development, Synopsys; YC Wong, Director of IC Engineering, Broadcom; Shrenik Mehta, Sr. Director of Frontend Tools and OpenSPARC, Sun Microsystems; Faisal Haque, Director of Engineering, Qualcomm; and Amit Chowdhry, Member of Technical Staff, AMD



VMM User Forum Lunch Event: NVIDIA

Engineering the APX2500: Verification Methodology for Low Power Watch a presentation on NVIDIA’s experience using the Verification Methodology for Low Power Design on the APX2500, the world’s lowest power, high definition video and graphics computer on a chip.
Soma Bhattacharjee, Director of Engineering



VMM User Forum Lunch Event: Renesas Technology Corporation

Low Power Verification User Experience See a presentation on the unique challenges of low power design verification and how they are being addressed by Reneses using Synopsys' tools.
Yoshio Inoue, Chief Engineer



VMM User Forum Lunch Event: ARM, Ltd.

Need for a Low Power Verification Methodology. Learn about ARM and Synopsys’ joint efforts to develop a Verification Methodology for Low Power Designs.
Alan Hunter, Verification Methodology Lead



VMM User Forum Lunch Event: IBM

"Are We There Yet?" Listen to a discussion on VMM Planner and how IBM used it on their BIST project to determine when they had run enough random tests.
Nancy Pratt, BIST Verification Lead




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