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Thought you had verified your SoC? You probably only did half...
Why do I say this? The major objective of SoC functional verification is to ensure that the design is performing its intended function correctly. This is usually done in simulation by creating lots of stimuli for the design under test, representing real use cases, and checking the responses.
Mar 29, 2016

Exploiting the power of reset in formal verification
The reset state of a module or SoC that is being verified can have a huge impact on the scope and correctness of the verification. When using simulation for verification, the reset phase is usually not a large concern.
Mar 29, 2016

Reachable or reached, covered or coverable – is it just semantics?
RTL code coverage is used to measure the progress of SoC functional verification for simulation, formal property verification (FPV) and other formal techniques, but have you ever wondered about how code coverage differs between the two?
Mar 29, 2016

Don’t over-constrain in formal property verification (FPV) flows
Formal property verification (FPV) is increasingly being used to complement simulation for system-on-chip (SoC) verification. Adding FPV to your verification flow can greatly accelerate verification closure and find tough corner-case bugs, but it is important to understand the differences between the technologies.
Mar 29, 2016

Synopsys at DVCon 2016
DVCon starts on Monday Feb 29th and as always should be a packed event. One of the most obvious things you will notice is Synopsys’ presence in the exhibit hall – they take up a complete side of the hall with stations running the gamut of functional verification: integrated verification solutions, simulation, static analysis, debug, verification IP, emulation and prototyping.
Feb 23, 2016

Debug Becomes A Bigger Problem
EDA companies have been developing more integrated debug flows that bring execution engines and hardware and software closer together, but is that enough?
Feb 11, 2016

Don’t Over-Constrain in Formal Property Verification (FPV) Flows
Formal property verification (FPV) is increasingly being used to complement simulation for system-on-chip (SoC) verification. Adding FPV to your verification flow can greatly accelerate verification closure and find tough corner-case bugs, but it is important to understand the differences between the technologies.
Feb 04, 2016

Domain Crossing Verification Needs Continue to Grow
Clock domain crossing (CDC) analysis has been around for many years, initially as special checks in verification or static timing analysis, but it fairly quickly diverged into specialized tools focused just on this problem.
Jan 29, 2016

Debug: Last Bastion Of Automation
Folklore erroneously claims verification consumes 70% of development time. But does debug really consume 50%?
Jan 27, 2016

Catching Complex CDC Bugs in Large SoCs
Much of the complexity of large SoC designs is due to the many signals that integrate the IP blocks into a cohesive whole – clocks, resets, and power-management signals. These present a verification challenge because they are often asynchronous to other parts of the design, and can cross in and out of clock, power and reset domains, leading to potential metastability issues that are hard to find and hard to fix.
Jan 20, 2016

Reachable or Reached, Covered or Coverable – is it Just Semantics?
RTL code coverage is used to measure the progress of SoC functional verification for simulation, formal property verification (FPV) and other formal techniques, but have you ever wondered about how code coverage differs between the two? There are clear similarities, but also large differences. The interpretation of the results is different, and by understanding and taking advantage of this difference, you can speed up coverage closure in simulation.
Jan 19, 2016

DesignWare Technical Bulletin: Memory Options for the IoT
Jan 12, 2016

How Not To Be Incoherent
The advantage of working with cache memory is the great boost in performance you can get from working with a local high-speed copy of chunks of data from main memory. The Synopsys VIP for the AMBA4 ACE and AMBA5 CHI protocols is an excellent example of why use of proven VIP is so important in testplans.
Jan 01, 2016

Chasing After Phantom Power
Demand for increasing functionality when products are off is being compounded by a growing number of products.
Dec 10, 2015

Perfecting the Great Verification Fugue
Michael Sanie, Senior Director Marketing in the Synopsys Verification Group, gave the wrap-up presentation at SpyGlass World recently, on the Synopsys Verification Direction.
Nov 03, 2015

Making IP Secure
The semiconductor ecosystem is beginning to identify security holes, what tools can be used to plug them, and what else is needed.
Nov 02, 2015

Gaps In Performance, Power Coverage
Coverage tells us when we have done enough functional verification, but what about power and performance? How do you know you have found the worst case?
Oct 15, 2015

Outbound Power Management
In the IoT era we will have to start looking at power in reverse.
Oct 15, 2015

SpyGlass World at Levi Stadium, October 21st
The day begins with a keynote from Philippe Magarshack, CTO of STMicroelectronics, followed by user experiences from Broadcom, Marvell, Infineon, and Xilinx.
Oct 12, 2015

Preparing for Low-Power Verification Success: Setting Objectives and Measuring Outcomes
Functionally verifying complex SoCs is an enormous challenge, and the challenge grows when multiple power domains are throttled or powered up and down for power management needs.
Oct 08, 2015

Verification platform offers unified compile, debug environments
Synopsys is integrating its verification offerings to help SoC designers get chips to market more quickly
Sep 29, 2014

Platform to speed design bring up and time to market for SoCs
Verification Continuum, developed in close collaboration with market leaders, will enable a new era of SoC verification for the industry
Sep 26, 2014

Synopsys Verification Continuum
Synopsys announced their Verification Continuum Platform
Sep 26, 2014

Transaction-Based Emulation Helps Tame SoC Verification
Semiconductor design is largely driven by the relentless pace of new product introductions balanced against the fear of avoiding the dreaded mask re-spin.
Sep 03, 2014





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