The key to high-performance transaction-based verification is the Bus Functional Model (BFM) that converts high-level messages on the testbench side into signal-level activity on the design side. The BFM must be synthesized in hardware and emulated next to the DUT in order to achieve both high transaction performance and perfect cycle accuracy. Historically, writing that BFM was the main challenge of transaction-based emulation, requiring expertise in both software and RTL design.
ZEMI-3 is a SCE-MI 2.0 compatible behavioral SystemVerilog compiler for transactor BFMs that makes it extremely easy to write cycle-accurate BFMs and exchange messages with a C++ or SystemVerilog testbench. It uses the familiar "DPI-C" construct from SystemVerilog, where each function call is a transaction that is automatically off-loaded into the emulation hardware.
- Automatic generation of RTL BFM from behavioral SystemVerilog
- Automatic detection of streaming for best performance
- Transactor code is more compact and easier to maintain
- Overall 10X productivity improvement compared to SCE-MI
Solutions: Transaction-Based Verification