ZeBu-Server is an extremely high capacity system emulator with the easy setup and debugging associated with emulation, and the best price/performance in the industry. Supporting multiple users, interfaces, and host computers, ZeBu-Server is a flexible, scalable, billion-gate capacity ASIC and SoC emulator. Providing high bandwidth and multi-MHz performance at any level, ZeBu-Server primarily aims at large-scale, multi-core chip and system emulation applications. It is ideal for the system-integration phase of the design cycle where multiple logic blocks, multiple chips, and embedded software all must be verified together.
Hardware design and software development teams can share the same system and design representation, and can easily collaborate when debugging complex hardware/software interactions. The net effect is that hardware/software integration takes place much earlier in the design cycle, thereby reducing silicon respins and accelerating time-to-market.
ZeBu-Server is the highest performance emulator in the market, while also offering the most cost-effective solution in a small footprint, thanks to its use of standard Xilinx Virtex5-LX330 FPGAs. The ZeBu compiler automatically handles any design, regardless of size, coding style, clocking scheme, or memory structure, making it easy to map even your largest designs. Transitioning to ZeBu is easy, thanks to its complete software infrastructure, which includes the largest, most comprehensive library of transactor models.
Download the ZeBu-Server Datasheet.
- Design capacity: Scalable to over 1 Billion ASIC gates; Up to 200GB DDR2 Design Memory
- Multiple users: Up to 49 users
- Emulation speed: Up to 10 MHz design clock (400MHz System Clock)
- High bandwidth test environment: PCI-Express connectivity to multiple host PCs provides high bandwidth for streaming transactors, software checkers, assertion output, and waveform generation
- Rapid setup: Completely automated compiler, starting from ASIC RTL, requiring no RTL modifications
- zFAST: ZeBu Fast Synthesis for high speed, parallel, incremental synthesis with memory inference and preservation of RTL names
- Memory compiler: Supports an unlimited number of ports, scriptable for easy ASIC library conversion
- Comprehensive debugging: Run-time access to all register & signals without recompilation; pre-compiled probes for high speed tracing and software-based checkers; synthesizable SystemVerilog Assertion (SVA) support
- Third-party verification and system level tool integration: co-simulation with commercial HDL simulators and ESL tools, integration with waveform viewers and interactive debuggers
Solution: Fast SoC Emulation
Solution: Transaction-Based Verification
Solution: Simulation Acceleration
Solution: ESL Co-emulation