ZeBu allows you to simulate and debug a design at very high clock frequencies. Transaction-Based Verification (TBV) provides a virtual test environment that lets you verify your design without connecting physical devices to verify interactions of your SoC design with the outside world. To quickly implement your virtual verification environment, Synopsys offers a large library of protocol-specific transactors and virtual devices.
- Speed: ZeBu transactors offer the highest performance on the market, providing both high bandwidth (data streaming between host and emulator) and low latency (rate at which messages can be processed by testbench/transactor).
- Reuse: ZeBu separates the implementation of the protocol(s) from the generation of test scenarios, such that transactors are reusable, and testbenches can be assembled easily from building blocks.
- Ease of use: You can either buy off-the-shelf transactors for most common protocols, or design your own if you have a unique interface/application. The main part of a custom transactor is the Bus Functional Model (BFM) or Finite State Machine (FSM) for your interface, which can be written in standard Verilog or VHDL RTL, or in behavioral SystemVerilog using ZEMI-3, Synopsys' transactor compiler. Most likely, you already have a similar piece of code that can be easily converted to act as a transactor.
- Data-center Compatible: The virtual test environment defined with ZeBu transactors and virtual devices is implemented in software and requires no physical access to the emulation hardware. Unlike traditional In Circuit Emulation (ICE), bringing up a different TBV environment does not require physical access to the emulator in a lab but can be achieved by downloading a new environment to the host in a remote data center.
Various languages can be used for the transaction-based testbench:
- C/C++/SystemC testbench: ZeBu transactors are adapted from the SCE-MI standard and follow a simplified/optimized API so that you can be up and running with only a few lines of code. An API fully-compliant with SCE-MI is also available if compatibility across emulation platforms is more important than performance.
- SystemVerilog testbench: ZeBu transactors can be integrated with SystemVerilog testbenches using the standard ZeBu API, the SystemVerilog DPI, a SystemVerilog class, and the Verification Methodology Manual (VMM) Hardware Abstraction Layer (HAL), also from Synopsys.
The ZEMI-3 Transactor Compiler from Synopsys also simplifies the creation of transactor FSMs, and has the added benefits of:
- Supporting behavioral constructs, such as implicit state machines, wait states and mixed clock edges
- Automatic implementation of the transactor communication infrastructure
- Performance optimization via streaming, prefetching
Performance and Accuracy
The concept of transactors has been used in verification for a long time. A layered testbench cleanly separates the high-level protocol functions (for instance reading and writing on a AHB bus) from the low-level implementation (toggling the control and data signals of the AHB bus). ZeBu takes the concept one step further by off-loading the low-level transaction encoding and decoding into dedicated, customizable hardware. That accomplishes two unique goals: cycle accuracy, high performance — on par with traditional in-circuit emulation (with live circuits).
Product: ZeBu Transactors and Memory Model Solutions
Product: ZEMI-3 Transactor Compiler