Most SoCs include one or more embedded processor cores. While ZeBu is a generic platform for hardware debugging of any SoC, certain optimizations and customization are available to better serve software developers and to ease the mapping of the processor models in emulation.
Instruction Set Simulators
Early SoC and SW development may leverage an Instruction Set Simulator (ISS) for the processor core, often written in C or SystemC, and operating at a higher level of abstraction than the SoC sub-system. An ISS can be integrated with ZeBu via a transactor (e.g. AMBA AXI) to provide a high-performance link to the rest of the emulated SoC.
Some embedded cores are available as soft IP, so their RTL will be processed directly by the ZeBu compiler, and emulated along with the rest of the SoC design. Other cores are only available as hard macros, in which case Synopsys offers various solutions to integrate those cores into a complete emulation project.
Synopsys also offers sample memory sub-systems so you can quickly build a software development platform, which you can later refine to include your entire SoC. In effect, those become equivalent to a fast ISS, running an order of magnitude or faster than a standard software ISS, and with perfect cycle accuracy since the model is the actual processor RTL.
Integration With Software Development Toolchains
Debugging software on the real SoC design is a key benefit of fast emulation. Synopsys has developed close partnerships with the embedded processor vendors to provide a closer integration between ZeBu and their software development toolchain. With ISS integration, SW debugging is available through the built-in ISS capabilities. For hard IP cores, a dedicated JTAG port would be used to connect to the SW debugger. A JTAG pod can also be leveraged for soft IP (RTL) cores, through ZeBu's Smart-ZICE or Direct-ICE interfaces. Alternatively for soft IP, Synopsys also offers the virtualization of interfaces, such as JTAG, Ethernet and UART, which enable seamless remote connections to the SW debugger.
Solution: ARM, MIPS, Tensilica, Synopsys (ARC) and Texas Instruments based SoCs
Solution: HW/SW Co-Verification