Hybrid emulation combines emulation and virtual prototyping to enable earlier architecture validation and software development, as well as higher performance for software-driven RTL verification even when critical IP RTL isn’t available. For the hardware architect, it enables RTL processor subsystems running in an emulator to serve as a high-performance, cycle-accurate model for SoC performance and architecture validation through cycle accurate interfaces to SystemC models of other blocks like memory controllers and subsystems in the virtual platform. For the software developer, instruction accurate models in the virtual prototype are used for software development with the remaining SoC design blocks run at high speed in the emulator. For the verification engineer, pre-verified processor subsystem blocks can be moved out of the emulator and executed on the host platform using a virtual prototype of the processor subsystem, freeing up capacity on the emulator while increasing overall performance.
ZeBu enables hybrid emulation through integration with SystemC/TLM2.0 virtual platforms including Synopsys Platform Architect MCO (PA MCO) and Virtualizer. The PA MCO and Virtualizer interface uses the graphical interface of Platform Creator to easily instantiate the model linking the virtual platforms with ZeBu. The ZeBu compiler can accept any RTL block, no matter how large or complex, and turn it into a virtual platform compatible model functioning at millions of transactions per second, thanks to ZeBu's high-performance emulation and transaction-based verification.
A generic TLM 2.0 transactor provides a standards based interface to any SystemC virtual platform environment to ease the integration effort of building such hybrid emulation platforms.
Download Datasheet: Hybrid Emulation
Solutions: Transaction-Level Verification
See also: Virtualizer