Embedded software plays a critical role in driving today's SoC verification at various stages. With growing SoC complexity and evolving processor architecture, it has become increasingly difficult to perform SoC debug activities. What is needed is a simultaneous view of both hardware and software languages to help designers efficiently and effectively advance their debug productivity.
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Verdi3 HW SW Debug
Synopsys' Verdi3™ HW SW Debug enables embedded software-driven SoC verification by providing a synchronized multi-window view of the design's behavior of both hardware and software languages. It combines an instruction-accurate embedded processor, RTL, C and assembly visibility for a comprehensive SoC debug solution. Verdi3 HW SW Debug is based on Verdi, the industry's open, most comprehensive debug platform with powerful technology that helps design and verification teams comprehend complex and unfamiliar design behavior, automate difficult and tedious debug processes and unify diverse and complicated design environments.
Figure 1: Verdi3 HW SW Debug using multi-window debug view
Figure 2: Verdi3 HW SW debug provides simultaneous views into multiple cores
- Comprehensive Multi-Window Debug View
The Verdi3 HW SW Debug works together with the Verdi3 Debug Automation System to provide a comprehensive multi-window hardware and software debug view of a SoC design (see Figure 1). When operating Verdi3's unified debug environment, both hardware and software engineers can simultaneously view their design at:
- RTL and gate level, including HDL source code, waveform, schematic, assertion, testbench, transaction and power-aware debug
- Programmer's view of both C/C++ and assembly code as well as memory, register and breakpoint windows
- Key Features
- Complete software debug views including
- Registers view
- Call stack view
- Variables view
- Memory view
- Fully synchronized hardware and software views: Jumping in any context in full simulation time range
- Forward, backward
- Statement in C, assembly source code
- Waveform value changes
- Selected simulation time
- Supports breakpoint setting in C, assembly
- Support simultaneous debug of multiple cores
- Support several families of ARM® cores as well as custom or proprietary cores
Figure 3: Software debug view in Eclipse UI
Fully Synchronized Hardware and Software Debug Views
With Verdi3 HW SW Debug, users can perform debug in either software or hardware views. When the simulation time cursor moves in the waveform, the corresponding software statement will be highlighted in the software view. Conversely, if a user is stepping the software statement in the software view, the simulation time in the hardware views will be automatically synchronized. Users can freely move forward or backward in the whole simulation time range. Users can also set up the break points to quickly jump to interested points.
Figure 4: Complete hardware debug automation functions based on Verdi3
Simultaneous Debug of Multiple Cores
Today, it has become almost impossible for SoC designers to correlate the simulation waveform and exact software instructions running in the core. The situation worsens when there are multiple cores in the SoC design, since along with multiple software, are execution threads. Verdi3 HW SW Debug provides a mechanism that automatically establishes the correlation between waveform and executed software instructions, and allows programmers to simultaneously view multiple cores (see Figure 2). Verdi3 HW SW Debug doesn't require special designed processor models, and it works with the regular simulation models with or without encryption.
Figure 5: Open and expandable architecture of Verdi3
Figure 6: Tool integration example based on Verdi3 platform
- Industry Proven and Open Infrastructure
Verdi3 HW SW Debug is developed on top of Verdi3 Debug Automation platform, the industry's open, most comprehensive debug platform with powerful technology that helps users comprehend complex and unfamiliar design behavior, automate difficult and tedious debug processes and unify diverse and complicated design environments.
- The software debug user interfaces are based on the popular Eclipse framework (see Figure 3)
- It provides software engineers a friendly use model
- All the existing hardware debug automation features in Verdi3 are fully supported including all languages and methodologies (see Figure 4)
Interoperability and Openness
The open architecture and interoperability of the Verdi3 platform enables users to leverage their investment with integration of other commercial and proprietary verification tools. Verdi3's continuously expanding ecosystem provides out-of-the-box support for a wide range of commonly used tools, including simulators, emulators, accelerators, model checkers and other formal analysis engines (See Figure 5).
Verdi3 HW SW Debug does not require the access to the sensitive micro architecture level information for custom or proprietary core. Thus, there is no concern with confidential information leakage in order to enable the HW SW debug capability with Verdi3.
Through FSDB and the VC Apps interface, users can easily integrate Verdi3 HW SW Debug with either Synopsys or third-party tools to improve design productivity. For example, it can easily work with either the Synopsys Protocol Analyzer or Platform Architect to provide complete design debug or analysis (see Figure 6).
Supported processor models include several families of ARM cores as well as custom or proprietary cores. Please contact a Synopsys sales representative on the latest supported embedded core list.