Synopsys delivers comprehensive verification solutions spanning the complete design cycle, including simulation and acceleration, emulation, advanced debug, static/formal verification, FPGA prototyping and virtual platforms. The combination of best-in-class technology, verification IP, advanced methodologies, open environments, and robust ecosystem enables you to solve the challenge of rapidly escalating SoC complexities, accelerate your development schedule with confidence, and bring compelling, innovative products to market more rapidly than ever before.
Visit Synopsys at Booth #201VCS Functional Verification SolutionDiscovery Verification IPVerdi Debug PlatformZeBu Emulation (Acceleration)HAPS FPGA Prototyping Solution
Visit Synopsys at DVCon 2013 to learn from the experts in verification and to see demos in the following areas:
Register now for DVCon 2013
Exhibit Dates and Hours
Tuesday, February 26: 3:30 - 6:30PM
Wednesday, February 27: 3:30 - 6:30PM
DoubleTree Hotel in San Jose, CA
|Synopsys customers and prospective customers:|
Join us on Tuesday night, February 26, 6:30 – 10:00 PM.
Become a Synopsys VIP for an evening of fun, food and entertainment at the San Jose Improv!
More details and registration
Synopsys Sponsored Luncheon
Also be sure to join us at the sponsored luncheon, SoC Leaders Verify with Synopsys, on Thursday, February 28, Noon – 1:30PM, in the Cascade/Sierra ballrooms.
Synopsys Conversation Central - DVCon Interview
Watch the latest Conversation Central show featuring DVCon's General Chair, Stan Krolikoski, and Technical Program Chair, Ambar Sarkar, and learn what's exciting about the 2013 conference.
|Date / Time||Session||Title / Speaker / Author(s)|
|POSTER||Switch the Gears of the UVM Register Package to Cruise through the Street Named "Register Verification"|
Abhisek Verma, Synopsys, Inc.
|POSTER||An Approach for Faster Compilation of Complex Verification Environment: The USB3.0 Experience|
Mahesha Shankarathota, Synopsys, Inc.
|POSTER||Verifying Functionality is Simply Not Enough!|
Rajesh Bawankule, Nokia Siemens Networks
|SESSION 4.4: Verification Process and Resource Management||Using Advanced OOP Concepts to Integrate Templatized Algorithms & Standard Protocols with UVM|
Anunay Bajaj; Gaurav Chugh, Synopsys, Inc.
|SESSION 8.2: Hardcore UVM - I||Beyond UVM: Creating Truly Reusable Protocol Layering|
Janick Bergeron; Steve Knoeck; Steven McMaster; Aaron Pratt; Kiran Maiya
|SESSION 8.3: Hardcore UVM - I||OVM to UVM: The Definitive Guide|
Adiel A. Khan, Synopsys, Inc.,
Justin Refice; Warren Stapleton, Advanced Micro Devices, Inc.
|SESSION 9.1: Mixed-Signal/Power Aware Design and Verification||A Systematic Approach to Power State Table (PST) Debugging|
Bhaskar Pal; Suman Nandan; Kaushik De; Rajarshi Mukherjee
|SESSION 10.3: Case Studies - II||Extendable Messaging Techniques for Debugging and Analyzing UVM Testbench Structure and Transaction Flow|
Jun Zhao; Rex Chen; Bindesh Patel
|SESSION 11.3: Hardcore UVM - II||C Through UVM: Effectively using C-Based Models with UVM-Based Verification IP|
Senay Haile, Qualcomm, Inc.
Kevork Dikramanjian; Abhisek Verma; Chris Spears, Synopsys, Inc.
|SESSION 12.3: PotPourri||Verifying Layered Protocols - Leveraging Advanced UVM Capabilities|
Amit Sharma; Parag Goel, Synopsys, Inc.
|TUTORIAL 2T||Increasing Productivity with SystemC in Complex System Design and Verification|
Nithya Ruff; Charu Khosla, Synopsys, Inc.
Trevor Wieman, Intel
David Black, Doulos
Shabtay Matalon; Jon McDonald, Mentor Graphics Corp.
Stuart Swan, Cadence
|TUTORIAL 3T||Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™|
Jeffrey Lee, Synopsys, Inc.
John Biggs, ARM, Inc.
Sushma Honnavara-Prasad, Broadcom Corp.
Dr. Qi Wang, Cadence
Erich Marschner, Mentor Graphics Corp.
|TUTORIAL 4T||User Experiences at the Forefront of Mixed-Signal Design and Verification|
Martin Barnasconi - NXP Semiconductors
Hélène Thibiéroz - Synopsys, Inc.
|TUTORIAL 7T||Higher-Level Verification IP (VIP) Capabilities Accelerate SoC Verification|
Neill Mullinger; Mansour Amirfathi;
Paul Graykowski; Pat Sheridan, Synopsys, Inc.
|LUNCHEON||Industry Leaders Verify with Synopsys|
Synopsys sponsored luncheon
|PANEL||Industry Leaders Panel: The Road to 1M Design Starts|
Moderator: JL Gray – Verilab, Inc.
Yervant Zorian, Synopsys, Inc.
Ziv Binyamin, Cadence
Serge Leef, Mentor Graphics Corp.
Sunil Shenoy, Intel Corp.