|Rethinking SoC Verification|
The industry is at an inflection point that calls for new, integrated verification solutions that will offer a fundamental shift forward in productivity, performance, capacity and functionality. Synopsys is meeting this demand with Verification Compiler™. Verification Compiler provides the software capabilities, technology, methodologies and VIP required for the functional verification of advanced SoC designs in one solution.
Rebecca Lipon, Synopsys
|Transaction Debug with Verdi|
SoC design is complex. It involves both software and hardware design that calls for a higher level of abstraction to ensure accurate verification. Transaction-level verification and debug offers this higher abstraction, while staying close to actual hardware signals. Traditionally, its use has been limited by the lack of a better mechanism and database to capture the critical information needed to do transaction debug, and a better way to view transaction data once captured. Through transaction debug, Verdi now enables users to maintain both the higher level of abstraction of a software debug environment with a direct connection to hardware signal data, thereby correlating their software and hardware debug approaches.
Rich Chang, Synopsys
|Enabling Synchronized Hardware Software Debug with Verdi³|
Verdi³™ HW SW Debug is an instruction-accurate embedded processor debug solution that offers fully synchronized views between hardware, as RTL or gate-level design models, and software, as C or assembly code — enabling co-debug between RTL and software.
Alex Wakefield, Synopsys; Joerg Richter, Synopsys
|Custom and Mixed-Signal Design Solution|
Synopsys’ unified solution for custom and cell-based design and verification provides a comprehensive, highly integrated suite of tools for advanced-node mixed-signal SoC design. The high degree of integration and interoperability shortens time-to-tapeout and improves design quality.
|Understand and Avoid Electromigration (EM) & IR-drop in Custom IP Blocks|
This whitepaper discusses the various trends exacerbating EM and IR-drop effects as well as design and analysis techniques to avoid them, and introduce Synopsys’ transistor-level analysis solution, which includes CustomSim for FastSPICE circuit simulation, StarRC for extraction, and Galaxy Custom Designer for custom layout.
Bradley Geden, Solutions Architect, Synopsys
|MOS Device Aging Analysis with HSPICE and CustomSim|
MOS Reliability Analysis (MOSRA) in HSPICE and CustomSim offers a robust and economic alternative
to empirical overdesign and extensive lifetime testing.
Bogdan Tudor, Joddy Wang, Weidong Liu, Hany Elhak, Synopsys
|Using Digital Verification Techniques on Mixed-signal SoCs with CustomSim and VCS|
A case study that explains the various aspects of a scalable and reusable methodology for verifying analog IP that can be applied to VMM/UVM, from verification planning to testbench implementation and coverage collection.
Graeme Nunn, Calvatec; Fabien Delguste, Adiel Khan, Abhisek Verma, Bradley Geden, Synopsys
|Accelerating Analog Simulation with HSPICE Precision Parallel Technology|
HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other full mixed-signal circuits. HPP addresses the traditional bottleneck in accelerating SPICE on multicore CPUs with new algorithms that enable a larger percentage of the simulation to be parallelized, with no compromise in golden HSPICE accuracy. Additionally, efficient memory management allows simulation of
post-layout circuits larger than 10 million elements.
Robert Daniels, Sr. Staff Engineer, Synopsys Inc.; Harald Von Sosen, Principal Engineer, Synopsys Inc.; Hany Elhak, Product Marketing Manager, Synopsys Inc.
|High-performance, Parallel Simulation with VCS Multicore Technology|
This white paper provides a detailed overview of VCS multicore technology, which improves verification performance by taking advantage of advances in the compute infrastructure. VCS multicore technology cuts verification time in half by harnessing the power of modern multicore CPUs and allows designers to identify performance bottlenecks and distribute time-consuming activities across multiple cores for faster functional verification and debug. Automatic partitioning and load balancing, event synchronization and memory optimization make VCS multicore unique for high-performance functional verification. Multicore technology combines the speed-up from parallel computation with the industry-leading Native Testbench (NTB) compiler optimization technique to deliver unmatched verification performance for large-scale designs for chip-level and system-level verification.
Usha Gaira and Sanjay Sawant
|Are We There Yet|
How do you know when you have run enough random tests? A constraint-driven random environment requires comprehensive coverage data, which often leads to information overload. Without an automatic way to associate pieces of coverage data with a particular feature-set in the test plan, the coverage report is only meaningful to the creator of the data.
|A Fully Reusable Register/Memory Access Solution: Using VMM RAL|
Register structure and memory modeling is a very complex task of any verification methodology. Building a zero time mirror to check the correct functionality of every field from every register and memory is usually a very time-consuming process which needs to be repeated for every design.
|Five Vital Steps to a Robust Testbench with DesignWare Verificatio IP|
Verification is one of the biggest challenges for System-on-Chip (SoC) designs, and traditional methods have run out of steam. Writing individual tests is impractical for today’s large, complex designs because the state space and number of test conditions is simply too large to code by hand, leading to insufficient test coverage.
|Low Power Verification for Multi-rail Cells|
Multi-voltage designs have become increasingly common in order to achieve low power. Multiple supply rails are an essential part of multi-voltage designs. Assuming that all output pins in a logic cone are related to a single supply voltage can cause functional failures in silicon or excessive power loss. Consequently, verification tools need to understand the relationship between the driving voltage rails and the impact on each output pin to accurately resolve the logic values. Synopsys’ Eclypse solution provides an infrastructure to capture the necessary information and MVSIM and MVRC are able to use the information to accurately verify multi-rail designs and lead to silicon success. This white paper discusses the challenges faced with static and dynamic verification of multi-rail cells in the context of low power designs.
Prapanna Tiwari, Synopsys, Inc.
|SystemVerilog for e Experts|
This document identifies the major differences between the e language as defined by the IEEE P1647/ D6 draft standard and the SystemVerilog language as defined by the IEEE Std. 1800™ 2005 standard. It explains the semantics of those differences and, where relevant, presents how similar functionality can be obtained using SystemVerilog.