|Feb 03, 2016||Synopsys Redefines Circuit Simulation with Native Environment|
Eliminates Need for Third-party Environment, Accelerates Analog Verification
|Nov 23, 2015||Synopsys Delivers Industry's First Ethernet 400G Verification IP for Next-Generation Networking and Communications Systems|
Native SystemVerilog Ethernet VIP Features Built-in Coverage, Verification Planning, Protocol-Aware Debug and Source Code Test Suites
|Nov 10, 2015||Synopsys Enables Next-Level of Productivity with Addition of System-Level Capabilities to Verification IP for ARM Cache Coherent Protocols|
Expands Comprehensive VIP library for ARM® AMBA® protocols with System-Level Test Suites, System Monitor, Protocol-aware Debug and Performance Analysis; Adds VIP for New AMBA 5 AHB5 Standard
|Nov 03, 2015||MEDIA ALERT: Synopsys, Customers and Partners Highlight Successes Designing ARM-based Products at ARM TechCon 2015|
Technical Sessions Feature Processor Optimization, IP, Software Security, Prototyping and Verification Solutions
|Jun 08, 2015||Synopsys' CustomSim Delivers 2X Circuit Simulation Speed-up |
New Partitioning Technology Enables Consistent Multi-core Scalability
|May 13, 2015||Synopsys' Verification IP for DDR4 3DS Enables DRAM Designs with Higher Density and Performance at Reduced Power|
Native SystemVerilog-based VIP for DDR4 3DS Expands Synopsys' Portfolio of Memory VIP and Offers Built-in Coverage, Protocol Checks, Verification Plan and Protocol-aware Debug
|Mar 12, 2015||Synopsys' New Verification IP for MIPI SoundWire Enables Audio and Control Interfaces in Low Power Designs|
Native SystemVerilog-based VIP for SoundWire Expands Portfolio of VIP for Mobile Applications and Offers Built-in Coverage, Verification Plan and Protocol-aware Debug
|Feb 06, 2015||ARM and Synopsys Collaborate On ARM Cortex-A72 Processor-based SoCs with IC Compiler II|
ARM and Synopsys Collaboration Enables Optimized Implementation of ARM Cortex-A72 Processor-based SoCs with IC Compiler II
|Feb 03, 2015||Synopsys’ New 25G/50G Ethernet Verification IP Enables Next-Generation Gigabit Designs|
Native SystemVerilog Ethernet VIP and Source Code Test Suites Enhanced with Built-in-Coverage and Support for Protocol-aware Debug
|Jan 21, 2015||Synopsys Expands Memory Verification IP Portfolio with UFS, UniPro and eMMC to Accelerate Verification Closure for Mobile Designs|
Expands Memory Verification IP (VIP) Portfolio to Include Key Titles for the Mobile Industry
|Oct 27, 2014||SK Hynix Accelerates Memory Development with Productivity-Enhancing Debug Apps on Synopsys Verdi|
VC Apps open APIs automate memory testbench generation and debug. SK Hynix, Inc. has addressed their debug challenges by adopting the Synopsys VC Apps open application programming interfaces (APIs) to directly link their internally developed test generation technology to the industry-leading Synopsys Verdi® debug solution and allow their design and verification teams to customize their debug experience and boost debug productivity.
|Oct 14, 2014||Synopsys Enables Superior Verification Planning and Coverage Analysis with Verdi Coverage|
Verdi Coverage enables users to understand project progress, manage regression data, launch verification jobs, track project trends, generate reports and ultimately optimize resource allocation. This solution addresses the growing challenge of verification closure for complex system-on-chips (SoCs) by introducing advanced technology that allows users to quickly create efficient verification plans, integrate third-party and user-defined metrics, link plans to requirement documents, and intuitively track project and test-level metrics across simulation, static checking, formal verification, VIP and FPGA-based prototyping.
|Sep 23, 2014||Synopsys Unveils Verification Continuum to Enable Next Wave of Industry Innovation in Software Bring-Up for Complex SoCs|
Next-generation verification platform to accelerate time-to-market by months. The Synopsys Verification Continuum platform accelerates industry innovation for earlier software bring-up and shorter time-to-market for advanced SoCs. Verification Continuum is built from Synopsys' market-leading and fastest verification technologies providing virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping and debug in a unified environment with verification IP, planning and coverage technology.
|May 28, 2014||Synopsys Bridges Design and Verification with Next-Generation Static and Formal Technology for Verification Compiler|
Synopsys announces the availability of its VC Formal comprehensive formal verification solution, and VC CDC and VC LP advanced static checking solutions. These solutions address the growing verification challenges of complex SoCs by introducing next-generation verification technology that finds bugs earlier, faster and more accurately, as well as accelerates root-cause analysis.
|Apr 23, 2014||Synopsys Announces Industry's First Complete LPDDR4 IP Solution for High-Performance, Low-Power Mobile SoC Designs|
PHY, Controller and Verification IP Deliver up to 3200 Mbps Speeds for High-End Smartphones and Tablets
|Mar 25, 2014||Synopsys Unveils Advanced Mixed-Signal Verification Initiative to Accelerate Regression Testing of Mixed-Signal SoCs|
Initial Components of Initiative Extend Proven Verification Methodology and Technologies for Mixed-Signal Applications
|Mar 04, 2014||Synopsys Introduces Verification Compiler to Enable 3X Productivity|
Synopsys Introduces Verification Compiler to enable 3X productivity and deliver next-generation software technologies for complete verification flow. Verification Compiler is a complete portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure to create a complete functional verification flow with a single product.
|Feb 25, 2014||Synopsys Delivers Industry’s Fastest Emulation System|
ZeBu Server-3 speeds hardware-software bring-up, OS boot and SoC verification by up to 4X for faster time-to-market on even the largest designs
|Feb 25, 2014||Imagination Technologies and Synopsys Collaborate to Enable Faster Emulation|
ZeBu Server-3 emulator achieves 3.5 MHz performance on PowerVR Series 6 GPU to speed driver development and SoC verification
|Oct 14, 2013||Synopsys and TSMC Collaborate to Deliver 16-nm Custom Design Reference Flow |
TSMC Certifies Analog/Mixed-Signal Products for 16-nm Design Requirements
|Mar 19, 2013||Micronas Standardizes on Synopsys’ Design and Verification Solutions for Automotive Designs|
Solutions Include Galaxy Custom and Digital Implementation, Discovery Verification Platform
|Feb 07, 2013||Latest Advances in FineSim Deliver Up to 2X Performance and Capacity Improvements|
Enhancements Accelerate Verification of Advanced-node Memory Designs
|Jan 30, 2013||Imagination Technologies Selects Synopsys as Advanced Verification Technology Partner|
Multi-year Collaboration Results in Deployment of Synopsys' Advanced Formal Debug Technology for Verification of PowerVR Graphics Intellectual Property (IP) Cores
|Jan 21, 2013||Freescale Boosts Verification Productivity with Synopsys Verification IP|
Companies extend system-on-chip (SoC) verification collaboration on simulation, debug and verification IP.