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Verification platform offers unified compile, debug environments
Synopsys is integrating its verification offerings to help SoC designers get chips to market more quickly
Sep 29, 2014

Platform to speed design bring up and time to market for SoCs
Verification Continuum, developed in close collaboration with market leaders, will enable a new era of SoC verification for the industry
Sep 26, 2014

Synopsys Verification Continuum
Synopsys announced their Verification Continuum Platform
Sep 26, 2014

Transaction-Based Emulation Helps Tame SoC Verification
Semiconductor design is largely driven by the relentless pace of new product introductions balanced against the fear of avoiding the dreaded mask re-spin.
Sep 03, 2014

Hybrid emulation for development, validation and verification
This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.
Aug 19, 2014

Hybrid Emulation
Emulation has changed qualitatively with the recent improvements in performance since this hybrid emulation environment now runs fast enough that it can form the basis for early software development.
Jul 25, 2014

Managing Complexity With Hardware Emulation
Full verification using traditional tools can take months to validate system performance and uncover bugs.
Jul 02, 2014

Hybrid Emulation Accelerates Architecture Optimization, Software Development, And Software-Driven Verification
Hybrid emulation enables cycle-accurate models to be run on a high-performance emulator as part of a virtual prototype for architecture optimization and early software development.
Apr 30, 2014

Emulation: 3B Gates, 3MHZ
Synopsys announced the next generation of the EVE platform, ZeBu 3
Mar 19, 2014

Synopsys’s Next Generation Emulation Server-3
Synopsys announced Zebu Server-3, currently the industry's fastest emulation system
Feb 28, 2014

Multi-Billion-Cycle Tests Require Comprehensive Debug
Semiconductor design is largely driven by the relentless pace of new product introductions balanced against the fear of avoiding the dreaded mask re-spin.
Feb 20, 2014

System-Level Design Roundtable from DAC 2013 Ed Sperling, part III
The Future Of Verification. How verification is changing; validation vs. verification; the limits of divide and conquer; the impact of stacked die; questions about whether the lines are blurring between board and die; permanent employment for verification experts.
Nov 11, 2013

Start Verification Early To Avoid Pitfalls Later
It is well understood – at least from a theoretical point of view – that design verification should start as early as possible. The reality is that that doesn’t always happen for a variety of reasons such as enormous time to market pressure, too many new features to add, lack of foresight and discipline among other things. But progress is being made.
Oct 24, 2013

Experts At The Table: Debug – Part II
What are the big issues with debug? Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation.
Oct 24, 2013

System-Level Design Roundtable from DAC 2013 Ed Sperling, part I
The Future Of Verification. Raising the abstraction level and the effect on verification time; productivity measurements; the need to start verification earlier; concurrent issues; talk about a productivity gap resurfaces.
Oct 24, 2013

Experts At The Table: Debug – Part I
First of three parts: Multi-contextual debugging; IP Integration issues and who to call when you got a problem; why it’s taking more time to debug; limitations of tools; attitudes of IP development teams to customer issues.
Sep 26, 2013

Finding A Bug In The SoC Haystack
Finding critical bugs in the interaction of the embedded software running with the underling hardware, is like finding the proverbial needle in a haystack.
Aug 09, 2013

Debugging Verification Constraints
Designs now can have 50-100K lines of constraints which leads to performance issues. The constraint solver under the hood of Synopsys's verification environment has been improved and that has sped things up, sometimes by as much as 25 times but more often just a factor of 2.
Jul 23, 2013

Software Debug gets tricky
Traditionally, emulation has played a significant role in verifying that software against RTL code, and continues to do so. But with the advent of multicore architectures, the picture is evolving.
Jul 11, 2013

TBV and emulation combine multi-megahertz verification performance
Design complexity has grown with each successive generation of system-on-chip (SoC) evolution.
Jun 17, 2013

Facing the Verification Management Challenge
The integration of multicore CPUs, graphics coprocessors, modems, multimedia and networking facilities in the SoCs that power today’s sophisticated smartphones, tablets, computing and networking devices is creating a new verification challenge.
May 23, 2013

Power Trumps performance in today’s SoC designs
Designing a complex embedded system-on-chip (SoC) today is a multi-pronged challenge.
May 02, 2013

Dealing with the Data Glut
Tools like emulation and simulation are an absolute necessity to design and verify today’s complex SoCs, but what happens when you want to do power analysis and the file sizes are too massive for the emulator to handle?
Apr 11, 2013

Generating AMD microcode stimuli using VCS constraint solver
In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. We present and analyze the method and discuss its effectiveness in today’s verification environment.
Jul 14, 2010





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