A more intelligent approach to verification can help design teams control the rising cost of chip design, according to Manoj Gandhi, senior vice president and general manager of Synopsys’ Verification Group.
Sep 13, 2010

In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. We present and analyze the method and discuss its effectiveness in today’s verification environment.
Jul 14, 2010

This two-part article series looks at a scalable constraint methodology and provides an overview of some of the key constraint optimization challenges and strategies of concern to verification engineers. Part 2 of this article series focuses on explores the similarities and differences, including subtle semantic differences, between E Soft Constraints and OpenVera Default constraints in the interest of optimizing constraint performance and speeding validation.
Mar 09, 2010

This two-part article series looks at a scalable constraint methodology and provides an overview of some of the key constraint optimization challenges and strategies of concern to verification engineers. Part 1 of this article series focuses on verification IP reuse—detailing how a solver typically interprets constraints and providing a case study focused on a constraint-driven performance optimization strategy with respect to the flexible packet parser of a hypothetical networking ASIC.
Mar 02, 2010

During the first EE Times System-on-Chip Virtual Conference, a panel on verification challenges raised pressing issues in the areas of cost, startups, impact of electronic sytem level (ESL) design, virtual plattforms and functional verification as a methodology.
Sep 17, 2009

SystemVerilog and VMM-based environment help achieve first pass silicon success by performing smarter verification quicker.
Aug 05, 2009

The latest generation of Synopsys’ Discovery verification platform upgrades the offering with new multicore simulation technologies, native design checks and low- power verification capabilities.
May 01, 2009

As compute infrastructures transition to multicore, multi-threaded architectures, verification solutions must evolve to optimize the performance on new hardware.
Apr 17, 2009

EDA industry is reeling under pressure to innovate. Semiconductor vendors are in no-mood to pay hefty charges for some small improvements. EDA vendors are left with limited options either to provide cost optimized solution or powerful high performance chip design software of 2x performance for same cost.
Apr 14, 2009

Synopsys is beefing up its Discovery verification platform, a move that is at the forefront of a projected recovery in the electronics industry and a new push for tools that can help ease the burden of increasingly complex SoC designs.
Apr 06, 2009

Platform Encompasses New Multicore Simulation Performance, Native Design Checks, Comprehensive Low Power Verification Capabilities, and CustomSim Unified Circuit Simulation Solution.
Apr 06, 2009

Synopsys has increased verification speed and brought digital, analogue and memory simulation under the same roof as it moves its tools to multi-core hosts.
Apr 06, 2009

We all want our next-generation Pocket Rocket to do new stuff (and do the old stuff better), as well as get smaller, run longer, and cost less. We also don't necessarily want to wait for the holiday season for it to hit the shelves. We gadget freaks are often rather impatient in that regard.
Sep 11, 2008

Let’s face it. Some designers refuse to learn a new language. Or, the prospect of learning object-oriented programming makes some people break out in hives.
Aug 26, 2008

Judging by advertising and datasheets and other promotional materials, verification is pretty much a simple, clear-cut, well-solved problem. Actually, that’s not quite true.
Aug 26, 2008

The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips.
Jul 06, 2006

Over the past 20 years, the level of abstraction for chip design has risen from transistors through gates and RTL to the electronic system level (ESL).
Jun 12, 2006

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks.
May 01, 2006

Today’s chip design requires extensive system-level simulations to ensure that the right architectural trade-offs are made. In most cases these simulations require that a substantial amount of software is executed on the simulation model of the chip to cover the required functionality.
Mar 06, 2006

At the SNUG (Synopsys Users Group) East meeting this week in Boston, Synopsys will release Pioneer-NTB, its new automatic testbench-verification system supporting the SystemVerilog design and verification language.
Sep 26, 2005

SAN FRANCISCO — The SystemVerilog Verification Methodology Manual (VMM), a book authored by verification experts from Synopsys Inc. and ARM Ltd. describing the use of SystemVerilog for verification, has been publish by Springer Science + Business Media Inc., the publisher said Wednesday (Sept. 21).
Sep 21, 2005

In the past few years, the semiconductor industry has been adding ever larger engineering resources to meet rapidly increasing functional verification challenges.
Jul 01, 2005

ANAHEIM, Calif. — A System Verilog Users' Forum here at the Design Automation Conference on Monday (June 13) gave a rare opportunity for users to speak out through the din of marketing messages that is growing over the battlefield between System Verliog and System C.
Jun 14, 2005

SAN FRANCISCO — Synopsys Inc. said Tuesday (May 31) that new capabilities added to its VCS register-transfer level (RTL) product can improve verification speed by up to five times.
May 31, 2005