By Gunnar Scholl, Product Marketing Manager, Synplicity Business Group at Synopsys
The complexity, performance and functionality of the chips required for today's and tomorrow's electronic products —such as music players, smart phones, camcorders or game consoles — is increasing significantly. The most critical, cost intensive and challenging tasks for design engineers are the chip verification and software development, often accounting for more than 75% of the overall design costs.
To stay competitive and meet time and budget constraints, especially in these days, design teams must keep up with the generational changes in semiconductor process technology, which requires adopting new design and verification methods.
To address the verification requirements of these increasingly complex chip designs EDA and semiconductor vendors need to create new approaches and methodologies for embedded software development and system validation. Traditional methods, such as pure simulation or "big-box" emulation may no longer be sufficient to address these challenges due to cost, portability and performance issues.
For instance the performance of traditional RTL simulators decrease rapidly for large ASIC designs and performance drops at precisely the point in the verification process that requires millions of clock cycles to adequately test and verify software functionality. At that performance, software debugging would take several months. Simulation accelerators and "big-box" emulators can increase the speed up to 2 MHz, but even that is in many cases still too slow for embedded software development and verification as well as for “real world interfaces” where performances beyond 10MHz are required.
More Comprehensive Verification On Transaction-Based Level
To achieve these kind of speed requirements new verification methodologies like transaction-based verification in combination with Rapid Prototyping systems are necessary.
Most of the co-simulation verification environments are working event- based, meaning that they have to provide data every clock cycle. This event-based mechanism is responsible for the low speed in the co-simulation mode and only allows a maximum speed in the kHz range. In contrast, the transaction-based verification mode accelerates the verification by allowing large amounts of data representing single or multiple clock cycles to be passed into simulation without multiple calls.
Through this mechanism the communication traffic of the events between the host (test-bench) and the hardware will be minimized, resulting in a dramatic speed-up for the verification and allowing to run real world applications like HDTV or real time phone calls, representing hundreds of millions of cycle per test case, in minutes.
Using SCE-MI - The Big Picture
The foundation for transaction based verification in combination with hardware assisted verification systems is Accellera’s Standard Co-Emulation Modeling Interface (SCE-MI) that defines a transaction-level testbench modeling style.
The SCE-MI interface supports testbenches written in C, C++, and SystemC languages to drive the hardware directly, which allows the user to verify his design without a simulator connected at runtime. The synthesizable RTL part of the transactor is moved into the hardware platform. The C/C++/SystemC code running on the workstation is interfaced to the hardware through the SCE-MI–based interface. This mechanism can deliver much higher performance than an HDL-based testbench.
CHIPit Transaction Based Verification Solution
With the combination of CHIPit automated Prototyping Systems and the SCE-MI Interface, Synopsys offers a transaction-based verification solution, which increases the overall performance and reduces the time-to-market dramatically.
The CHIPit SCE-MI Transaction-Based Verification package is seamlessly integrated into CHIPit software environment and provides an ease to use implementation flow. The tool set creates a transaction level verification environment, with the Design Under Test (DUT), which has to be mapped on the FPGAs in the CHIPit system, being stimulated from the host side by a C/C++ or System C test-bench. With the Infrastructure Linker the user can easily implement the SCE-MI communication infrastructure between the hardware side (CHIPit Prototyping System) and the software side (host). The SCE-MI interface, which is implemented over the patented, high bandwidth / low latency UMRBus Communication System, also enables the CHIPit debugging features, like the Host Controlled Debugging Tool. With these tools it is possible to dump the current states of registered signals inside the FPGA and show them in a wave form viewer.
Transaction based verification is not totally new and is already being used with traditional verification tools and methodologies for several years, but it is new and extremely powerful in combination with a High-Speed Rapid Prototyping Systems, like the CHIPit system. The architecture of a FPGA based prototyping system allows running a design in the range of 20 to 100 MHz. By integrating the transaction based verification environment into a prototyping system and by using transactions instead of signals, the prototyping system is now able to run at full speed — in the range of several MHz — without sacrificing accuracy and enabling to faster than any shorten the overall design time significantly.