SpyGlass New Feature Update (Japanese)
Learn about the latest key feature updates for the SpyGlass version 5.5.0 and 5.6.0 family of products including SpyGlass Lint, SpyGlass CDC, SpyGlass Constraints, SpyGlass Power, and SpyGlass DFT.
Kenichi Komiya, Verification CAE, Synopsys
Jun 01, 2016
Make your Coverage Closure SMARTer with Verdi – A Primer on Verification Planning and Coverage Modeling
In Part I of a multi-part webinar series on Verification Planning and Coverage, we will focus on how verification planning using Verdi Coverage can help make your coverage closure goals SMART.
Vaishnav Gorur, Product Marketing Manager, Verification Group & Bart Thielges CAE, Coverage and Planning, Verification Group, Synopsys
May 18, 2016
Xilinx and Synopsys Present: Meeting Test Goals Faster with SpyGlass DFT ADV
Early detection of testability issues can prevent major bottlenecks downstream and avoid time-consuming design iterations. In this webinar, Synopsys presents new techniques and capabilities available in SpyGlass DFT ADV such as high-impact test points to boost coverage, reduce the number of patterns, and minimize test costs. Our guest speaker from Xilinx discusses test challenges associated with large SoC designs such as the Xilinx Zynq® UltraScale™ chip family, and illustrates how SpyGlass DFT ADV addresses testability issues early in the design flow, saving weeks of complex DFT-related ECOs.
Amit Majumdar, Principal Engineer, Xilinx; Anthony Joseph, Applications Engineer, Synopsys; Dmitry Melnik, Marketing Manager, Synopsys
Apr 28, 2016
Increasing Verification Closure Effectiveness with Formal Verification
Learn about Synopsys VC Formal advanced techniques and formal coverage metrics that provide better convergence and simulation-like visibility, to achieve formal verification signoff.
Prapanna Tiwari, Formal Verification Product Marketing, Synopsys; Sean Safarpour, Ph.D., Formal Verification CAE Manager, Synopsys
Apr 20, 2016
Evolution of Socionext’s Golden UPF Design Flow for Achieving Power Efficiency
Learn about Socionext’s ever-evolving UPF design flow and their experience with successfully deploying a Golden UPF-based methodology using Synopsys tools.
Mahiro Hikita, Manager, Design Department II, SoC Design Division, Socionext, Inc.
Apr 07, 2016
Evolution of Socionext’s Golden UPF Design Flow for Achieving Power Efficiency (Japanese)
Learn about Socionext’s ever-evolving UPF design flow and their experience with successfully deploying a Golden UPF-based methodology using Synopsys tools.
Mahiro Hikita, Manager, Design Department II, SoC Design Division, Socionext, Inc.
Apr 07, 2016
What’s Next in Storage: NVMe Verification IP
In this webinar, we will discuss the latest technology in storage protocols, NVMe, a rapidly evolving high performance storage standard developed to reduce latency and support parallelism.
Eric Peterson, Senior R&D Engineer, Synopsys; Paul Graykowski, Senior Corporate Application Engineer (CAE) for Verification Group, Synopsys
Feb 23, 2016
Synopsys and TSMC Get Smart with Bluetooth for IoT SoCs
Learn about the growing IoT market trends, the required wireless connectivity and new process technologies to achieve low-power consumption and enable efficient connectivity between devices.
Manuel Mota, Technical Marketing Manager, Synopsys; Leon Chang, Program Manager, TSMC
Feb 03, 2016
Catching the Uncatchable Bugs with SpyGlass CDC: Comprehensive, Practical, and Powerful Analysis
In this webinar, we will discuss how the SpyGlass CDC solution enables comprehensive clock and reset domain crossing (CDC/RDC) verification for more than a billion gates, helping designers to avoid costly chip killer bugs, re-spins and achieve signoff quality verification.
Kiran Vittal, Director Product Marketing, Verification Group, Synopsys; Sean O’Donohue; Senior Corporate Application Engineer (CAE), Verification Group, Synopsys
Jan 26, 2016
Raising Design and Verification Productivity with SpyGlass Lint Advanced: The Next Generation of Lint
In this webinar, we will discuss how the newly introduced SpyGlass Lint Advanced solution identifies RTL issues at their source, pinpoints structural, coding and consistency problems in the RTL descriptions, and helps designers resolve issues quickly before design implementation.
Arbind Kumar Rohilla, Verification Group, Synopsys
Dec 08, 2015
Securing Your IoT Processor Based System
This webinar will provide insight into IoT edge device security requirements and how they can be met with an ultra-low power processor.
Angela Raucher, Product Line Manager, ARC EM Processors, Synopsys
Dec 03, 2015
Impact of IP Reliability, Functional Safety & Quality in Automotive ADAS SoCs
Learn about ISO 26262 and AEC Q100 standards; latency, power, reliability and process-related design challenges; and how certified IP helps ensure functional safety, reliability and quality management.
Ron DiGiuseppe, Senior Strategic Marketing Manager, Synopsys
Dec 02, 2015
A Holistic Approach to Verification: Synopsys VIP for ARM AMBA Cache Coherent Interconnects
In this webinar, we will discuss how to take advantage of the system-level capabilities of Synopsys Verification IP for ARM® AMBA® protocols to verify cache-coherent interconnects. Synopsys VIP includes system-level interconnect test suites and system-level coverage to accelerate verification closure.
Satyapriya Acharya, Engineering Manager, Verification Group, Synopsys
Nov 18, 2015
Using Foundation IP in Low-Power 40nm IoT Designs (Mandarin)
This webinar will provide details on how foundation IP - logic libraries and embedded memories - can help designers of IoT applications take advantage of the power benefits available in 40nm processes.
Xueheng Ren, Senior Field Application Engineer, Synopsys
Oct 20, 2015
Identifying and Resolving Low Power Issues Before Tapeout
This webinar highlights how to find low power issues during verification using Formality.
Bob Hatt, Staff Corporate Applications Engineer, Synopsys
Sep 29, 2015
20X Power Analysis Performance Improvement with Synopsys Verdi Technologies
Discover how Synopsys' Verdi technologies, Siloti Correlation and Siloti What-If Replay Simulation, can enable up to 20X performance improvement for power analysis – from weeks to hours. These technologies enable the use of RTL simulation results to generate gate-level simulation data without the need to bring up the gate-level environment, thus enabling power analysis at early stages of the design cycle. Also included is parallel run technology to enhance performance up to 60X compared to the original flow.
Rich Chang, Product Marketing Manager, Debug, Synopsys
Sep 16, 2015
Learn How to Accelerate Verification Closure with PCIe Gen4 VIP
This webinar shows how to leverage protocol, methodology, verification and productivity features of Synopsys VC VIP and UVM source code test suites for accelerated verification closure of PCIe Gen4 based designs.
Paul Graykowski, Senior Manager, PCIe VIP, Synopsys
Aug 19, 2015
Using Foundation IP in Low-Power 40nm IoT Designs
This webinar will provide details on how foundation IP - logic libraries and embedded memories - can help designers of IoT applications take advantage of the power benefits available in 40nm processes.
Kenneth Brock, Product Marketing Manager, Logic Libraries, Synopsys
Jul 21, 2015
Addressing Verification Challenges of Evolving Ethernet Speeds from 25/40/50/100G and Beyond
We will outline in detail the verification challenges of current and future Ethernet speeds and explain how Accellera UVM Methodology, IEEE 1800-2012 System Verilog Functional Coverage, and SystemVerilog Ethernet Verification IP empowers design and verification teams with methodology, techniques and tools they need to achieve success.
Shenoy Mathew, Senior Corporate Applications Engineer, Verification Group, Synopsys
May 20, 2015
Picking up the pieces: self-contained verification platforms for the modular smartphone era
In the framework of Mobile platforms, learn how source code testsuites provided with Verification IP enable verification engineers to quickly generate diverse permutations of random/constrained random transactions that stress test the systems and subsystems, contributing to "Shift Left" of the verification time and ensure bug free designs.
Nitin Agrawal, CAE Manager, Verification Group, Synopsys
Apr 07, 2015
An Approach for Efficient IP Reuse in a Hierarchical UPF Methodology
This webinar will help you understand a Liberty-based approach for effective IP reuse in implementation of a multi-voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Feb 26, 2015
Achieving Energy Efficiency for IoT Designs
Learn how new investments in IP help improve system power usage and energy efficiency and enable added functionality for IoT applications including wearable and machine-to-machine devices.
Ron Lowman, Strategic Marketing Manager for IoT, Synopsys
Jan 27, 2015
Avoiding the Common Pitfalls of ARM-based Cache-coherent Verification and Performance Analysis
Synopsys will cover how verification IP for AMBA enables users to generate correct and interesting coherent stimulus for cache coherent SoC verification. This will include the complexities of configuration, stimulus, coverage and checking, as well as how to address the common verification pitfalls.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Tushar Mattu, Corporate Application Engineer (CAE) for Verification Group, Synopsys
Dec 03, 2014
LPDDR4 Multi-Channel Architecture
Learn about connecting multiple channels of DRAM, tradeoffs in SoC floorplans, logical to physical addressing, connecting to on-chip buses, and low-power design methods for LPDDR4.
Marc Greenberg, Director of Product Marketing for DDR Controller IP, Synopsys
Dec 02, 2014
High-Speed Embedded Linux Processing on an Embedded Power Budget
This webinar will look at a new high-speed processor implementation that can bring high-performance to your Linux-based embedded designs while significantly reducing power consumption.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Nov 06, 2014
The 10 Things to Know About Memory Verification: Synopsys Memory VIP
Learn how feature-rich, native SystemVerilog memory VIP rapidly verifies the memory interfaces on complex designs, focusing on 10 key areas where productivity is improved.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Nasib Naser, PhD, Senior Staff Corporate Applications Engineer, Synopsys
Oct 23, 2014
Reinventing Coverage and Planning with Verdi—A Fully Integrated, Complete Verification Closure Flow To Help You Deliver Chips On Time
The Synopsys Verdi® Coverage solution provides comprehensive planning and coverage analysis technologies as a part of the industry-leading Verdi3™Automated Debug System. We'll discuss why Synopsys' native integration of planning, coverage, and debug technologies provide a complete closure solution to help meet demanding schedules and provide teams with more confidence when asked the inevitable question: '"Are we done yet?"
Steve Chappell, Senior Product Marketing Manager, Debug and Analysis, Synopsys; Michael Horn, Verification Technologist, Synopsys
Oct 14, 2014
Addressing IP Compliance Challenges with UVM-based Test Suites
Protocol verification is a massive time- and resource-consuming endeavor, fraught with complexity and the risk of errors and omissions. Synopsys Verification Test Suites leverage the expertise of protocol experts to provide a rapidly deployable and extensible set of comprehensive tests, written in easily modifiable and reusable SystemVerilog UVM source code. The webinar will give an overview of the architecture and scope of Synopsys’ Verification Test Suites to achieve faster and higher quality coverage closure.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Karim Aoua, Staff CAE, Synopsys
Sep 30, 2014
How to Develop Ultra-Low Power Voice Control and Sensor Devices for Always-On IoT Apps
Learn how the efficient response and low power consumption of the ARC® EM DSP processor and Sensory TrulyHandsfree™ software solution deliver excellent performance with long battery life for IoT apps.
Paul Garden, Product Marketing Manager, Synopsys; Bernard Brafman, Vice President of Business Development, Sensory
Sep 18, 2014
Imagination and Synopsys: Reduce Dynamic Power and Area up to 50% on a GHz+ MIPS Core Implementation
In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014
Using a Golden UPF Methodology for Low Power Designs
This webinar will help you understand the best practices for implementation of a Golden UPF flow for Multi-Voltage designs using the IEEE 1801 (UPF) standard.
Somil Ingle, Sr. Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Apr 03, 2014
VCS Xprop: Catch X-Related Issues at RTL to Reduce Time-Consuming Gate-Level Simulations
In this webinar you'll learn about a new technology in VCS, called Xprop, which eliminates 'x' optimism at RTL to enable correlation with hardware design behavior. Xprop can be used to reduce and potentially eliminate gate-level simulations for 'x' validation. This webinar will also show how VCS® Xprop eliminates 'x' optimism in advanced simulation flows (such as VCS-NLP) and demonstrate how to debug 'x'-related issues identified by VCS-NLP and Xprop using Verdi™ Power-Aware Debug.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys
Nov 05, 2013
Verilog-to-Verilog Equivalence Checking Using ESP
This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed.
Philip Schmidt, R&D Manager, Synopsys; Dave Hedges, Corporate Applications Engineer, Synopsys
May 29, 2013

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