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Verification platform offers unified compile, debug environments
Synopsys is integrating its verification offerings to help SoC designers get chips to market more quickly
Sep 29, 2014

Platform to speed design bring up and time to market for SoCs
Verification Continuum, developed in close collaboration with market leaders, will enable a new era of SoC verification for the industry
Sep 26, 2014

Synopsys Verification Continuum
Synopsys announced their Verification Continuum Platform
Sep 26, 2014

Transaction-Based Emulation Helps Tame SoC Verification
Semiconductor design is largely driven by the relentless pace of new product introductions balanced against the fear of avoiding the dreaded mask re-spin.
Sep 03, 2014

Hybrid emulation for development, validation and verification
This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.
Aug 19, 2014

Hybrid Emulation
Emulation has changed qualitatively with the recent improvements in performance since this hybrid emulation environment now runs fast enough that it can form the basis for early software development.
Jul 25, 2014

Managing Complexity With Hardware Emulation
Full verification using traditional tools can take months to validate system performance and uncover bugs.
Jul 02, 2014

Hybrid Emulation Accelerates Architecture Optimization, Software Development, And Software-Driven Verification
Hybrid emulation enables cycle-accurate models to be run on a high-performance emulator as part of a virtual prototype for architecture optimization and early software development.
Apr 30, 2014

Emulation: 3B Gates, 3MHZ
Synopsys announced the next generation of the EVE platform, ZeBu 3
Mar 19, 2014

Synopsys’s Next Generation Emulation Server-3
Synopsys announced Zebu Server-3, currently the industry's fastest emulation system
Feb 28, 2014

Multi-Billion-Cycle Tests Require Comprehensive Debug
Semiconductor design is largely driven by the relentless pace of new product introductions balanced against the fear of avoiding the dreaded mask re-spin.
Feb 20, 2014

System-Level Design Roundtable from DAC 2013 Ed Sperling, part III
The Future Of Verification. How verification is changing; validation vs. verification; the limits of divide and conquer; the impact of stacked die; questions about whether the lines are blurring between board and die; permanent employment for verification experts.
Nov 11, 2013

Start Verification Early To Avoid Pitfalls Later
It is well understood – at least from a theoretical point of view – that design verification should start as early as possible. The reality is that that doesn’t always happen for a variety of reasons such as enormous time to market pressure, too many new features to add, lack of foresight and discipline among other things. But progress is being made.
Oct 24, 2013

Experts At The Table: Debug – Part II
What are the big issues with debug? Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation.
Oct 24, 2013

System-Level Design Roundtable from DAC 2013 Ed Sperling, part I
The Future Of Verification. Raising the abstraction level and the effect on verification time; productivity measurements; the need to start verification earlier; concurrent issues; talk about a productivity gap resurfaces.
Oct 24, 2013

Experts At The Table: Debug – Part I
First of three parts: Multi-contextual debugging; IP Integration issues and who to call when you got a problem; why it’s taking more time to debug; limitations of tools; attitudes of IP development teams to customer issues.
Sep 26, 2013

Debugging Verification Constraints
Designs now can have 50-100K lines of constraints which leads to performance issues. The constraint solver under the hood of Synopsys's verification environment has been improved and that has sped things up, sometimes by as much as 25 times but more often just a factor of 2.
Jul 23, 2013

Facing the Verification Management Challenge
The integration of multicore CPUs, graphics coprocessors, modems, multimedia and networking facilities in the SoCs that power today’s sophisticated smartphones, tablets, computing and networking devices is creating a new verification challenge.
May 23, 2013

Debugging the Debug Challenge
Around 70% of the effort involved in taping out a complex SoC is spent on verification. Of that effort, about half, or 35% of the total effort involved in a chip design, is spent on debug.
Apr 04, 2013

In Compliance We Trust, for Integration We Verify
So, you dropped that piece of complex IP you just licensed into a SoC design, and now it is time to fire up the simulator. How do you verify that it actually works in your design? If you didn’t get verification IP (VIP) with the functional IP, it might be a really long day.
Mar 26, 2013

Using VIP for Cache Coherency Hardware Implementations
For multi-core SoCs, engineers have typically implemented cache coherency protocols in software. The shift to higher-performance, lower-power designs has led to an increasing preference for hardware implementations.
Feb 05, 2013

Verification IP: The Questions You Should Ask
Drop-in verification IP is a mythical creature: Unlike design IP, VIP users don’t have the luxury of ‘drag and drop’ implementations that require relatively little protocol expertise on the user’s part. Verification engineers need protocol knowledge to check that coverage is complete, properly interpret results and debug unexpected behavior.
Jan 24, 2013

Verdi: No Requiem for Openness
Verdi is probably the industry's most widely used debug system, widely used in verification groups. Historically it has been a very open system, not restricted to any one verification environment.
Jan 22, 2013

The Industry Needs to Invest More in Debug
For the past few years, nearly all surveys have identified design debug as one the toughest challenges faced by system-on-chip (SoC) developers. According to data collected by Synopsys from leading SoC, processor, graphics and networking designs, 35 percent of the engineering time and effort for a project typically is spent on debug.
Sep 18, 2012





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