Writing tests to verify protocols is time consuming, challenging and requires deep protocol and methodology expertise. Synopsys testbenches help eliminate the task of writing compliance tests for today’s complex protocols.
The Test Suite for USB comprises a series of complete self-contained, configurable environments targeted at the verification of USB 3 and USB 2 based designs. It is provided as SystemVerilog UVM source code to simplify integration, enable user customization and maximize reuse across projects.
Test Suite Features:
- Provided as source code SystemVerilog UVM
- Support for USB 3.0 hosts and devices at PIPE and Serial interfaces
- Support for USB 2.0 hosts and devices at Serial, UTMI, ULPI and HSIC interfaces
- Test plan to track pass/fail status referenced to USB specifications
- Built-in coverage mapped to test plan
- Built-in data integrity checks