Synopsys Verification IP for SAS 


The Serial SCSI (SAS) System Verification Component (SVC) is designed to thoroughly verify your design using both random and directed simulation. The SAS SVC provides full SAS functionality and includes application layers that vastly simplify testbench development. Application layers provide simple APIs to generate SAS traffic: a SCSI application layer, an STP Host Exerciser and Management application layer. The SAS SVC supports constrained-randomization parameters throughout the layers to aid in coverage during testing. The SVC is implemented to be verification methodology neutral, and can be integrated with and controlled by any hardware verification language (e.g. SystemVerilog, UVM, C/C++, Vera, Specman, or Verilog). The SAS SVC supports all popular simulators.

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Primary Features
  • Supports all speeds up to 12 Gb
  • OOB sequence generation and checking
  • Initiator and Target models
  • Full Expander models, including SMP port
  • Supports speed negotiation, training, and multiplexing at any link speed
  • SCSI Application level exerciser for both unit and system level testing
  • Optional STP support with ATA Application level exerciser
  • Scalable for multiple instantiations to test multi-port hosts or devices
  • Checkers verify protocol timing checks and functional accuracy at each layer
  • Configurable pattern generation for random, directed or erroneous patterns
  • Built-in error injections for common cases
  • Constrained-randomized parameters aid in coverage during randomized testing
  • Statistics reported at each level to help determine corner case coverage
  • User call-backs and hooks for use in directed tests
  • Supports all major simulators

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