Synopsys Verification IP for Fibre Channel 

 

Overview
The Fibre Channel System Verification Component (SVC) is designed to thoroughly verify Fibre Channel designs using both random and directed simulation. The Fibre Channel SVC provides full protocol functionality and includes application layers that vastly simplify testbench development. Application layers provide simple APIs to act as a SCSI initiator, SCSI target or as a User-defined appication. Constrained-randomization parameters exist throughout the layers to aid in coverage during randomized testing. The SVC is verification methodology neutral, and can be integrated with and controlled by any hardware verification language (e.g. SystemVerilog, C/C++, Vera, Specman, or Verilog). The Fibre Channel SVC runs on all popular simulators. Created by recognized Fibre Channel experts involved with FC standards since 1992.

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Primary Features
  • Supports any speed, including 8Gb/10Gb
  • XAUI and 16Gb/s included
  • Supports L, N, and F ports
  • SAM-4 Application level exerciser for both unit and system level testing
  • Supports multiple instantiations to test multi-port hosts, switches or devices
  • Configurable pattern generation for random, directed or erroneous patterns
  • Constrained-randomized parameters to aid in coverage during randomized testing
  • Statistics reported at each level to help determine corner case coverage
  • Callbacks and hooks for use in directed test writing
  • Full Initiator and target models
  • Includes the following transactor interfaces for directed testing:
    • 10 or 20 bit Phy interfaces
    • 8 bit Encoder/Decoder interface
    • 32 bit Dword Primitive interface
    • Dword level transport interface
    • Complete Frame transaction level interface
  • Supports all major simulators



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