Synopsys Verification IP for NVM Express 

The Non-Volatile Memory Express (NVMe) System Verification Component (SVC) is designed to help thoroughly verify NVMe designs using both random and directed simulation. The Synopsys NVMe verification IP (VIP) component adds an application interface to the Synopsys PCI Express SVC. The NVMe protocol application enables host software to communicate with non-volatile memory subsystems, such as a Solid State Drive (SSD) or vice versa. The NVMe SVC is organized into three layers: the NVMe Command, the Host-Queuing and the (PCIe) Protocol Layers. The NVMe VIP requires the Synopsys PCI Express SVC. The VIP is implemented to be verification methodology neutral, and can be integrated with and controlled by any hardware verification language such as SystemVerilog (including UVM), C/C++,Vera, Specman or Verilog. The Synopsys SVCs run on all popular simulators.

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Figure 1

Primary Features
  • Commands supported:
    • Create Admin and I/O Queues
    • Identify — Controller and Namespace
    • NVMe Read and Write commands
  • Multiple Controller support
  • Multiple I/O Queues
  • User configurable queue size and configuration
  • Namespace configuration
  • PRP and PRP List support
  • MSI-X Interrupts
  • Protection Information (PI)
  • DIF/DIX (in-band/out-of-band) meta-data
  • Adjustable host page size support
  • PI Types 0 — 3 supported
  • Configurable LBA, length and command priority
  • Automatic host memory allocation and management
  • Supports all major simulators

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