MIPI HSI Verification IP 

The Synopsys Verification IP (VIP) for MIPI HSI is a comprehensive VIP solution enabling pre-silicon functional verification of MIPI HSI (High-speed synchronous Serial Interface) compliant designs. The Synopsys VIP allows design and verification engineers to quickly and extensively test the entire functionality of their MIPI HSI compliant designs. Availability of Test Suites enables the designer to focus on features unique to their design, and to verify their differentiators easily. The Synopsys VIP leverages advanced verification techniques in creating a versatile testbench environment.

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Figure 1
SoC verification environment

Primary Features
  • Compliant to MIPI HSI Physical Layer Version 1.01.00 specifications
  • Backward compliant to MIPI HSI Serial Interface Version 1.0 specifications
  • Supports all control channel commands (32-bit)
  • SystemVerilog Assertions (SVA)-based protocol checker
  • Includes wide variety of error injection and detection capabilities
  • On-the-fly protocol checking
  • Supports SystemVerilog OVM
  • Supports all major simulators

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