VC Verification IP for MIPI M-PHY 

 

Overview
Synopsys VC Verification IP for MIPI M-PHY provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of M-PHY links operating in high speed and low speed modes.

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VC MIPI M-PHY Verification IP



MIPI M-PHY Protocol Features

Supports MIPI ALLIANCE specification for M-PHY version 3.0.r6 – 26 July 2013
M-PHY Layer (L 1.0) Features
  • Interfaces
    • SERIAL-SYS and PWM signaling
    • RMMI – controller and PHY
  • TYPE_I and TYPE_II MODULE
  • HS and LS GEARS

M-PORT LM Layer (L1.5) Features
  • Configurable number of lanes
  • Supports asymmetrical lanes between TxSubLink and RxSubLink
  • Lane alignment at symbol boundary
  • Lane splitting and merging
  • Configurable number of frames
  • FILLER insertion
  • Lane-to-Lane skew
  • M-PORT LM layer system monitor
  • Configure VIP as MPHY model

CTRL and DATA SAP Interface
  • Interface with protocol adaptor layer
  • Independent port/channel for CTRL and DATA SAPs
  • All capability and configuration attributes
  • LS – HS mode change
  • HS - LS mode change
  • Gear change
  • External/internal SYNC support
  • Automatic FILLER insertion
  • User specific INITIAL state to start the simulation (other than DISABLED)



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