Discovery Verification IP for UART 

 

Overview
The Discovery™ Verification IP (VIP) for UART provides support for all speeds and data widths. It has a comprehensive set of protocols, methodology, verification and ease-of-use features, enabling users to achieve rapid coverage closure for their UART designs. Discovery VIP for UART is integrated with the Discovery Protocol Analyzer, a protocol-aware debug environment that enables users to quickly debug protocols by raising the abstraction level, and providing easy navigation through layers of the protocol hierarchy. Discovery VIP for UART is written entirely in SystemVerilog enabling it to run natively in supported simulators for highest performance. Its SystemVerilog architecture includes native support for UVM and built-in functional coverage.

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Discovery VIP for UART



Primary Features
  • Configurable Baud Rate Divisor
  • Configurable data-width with 5, 6, 7, 8 and 9-bits
  • Supports full-duplex
  • Supports line break generation and detection
  • Provides hardware, or out-band, flow control
  • Provides software, or in-band, flow control
  • Supports 1 and 2 stop bits, parity (even, odd)
  • Provides receiver FIFO with configurable depth
  • Built-in verification plan
  • Built-in functional coverage
  • Built-in monitor and checker
  • Includes error injection
  • Integrated with Protocol Analyzer
  • Supports System Verilog UVM, OVM testbenches
  • Supports all major simulators



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