PCIe Verification IP 


PCI Express (PCIe) Verification IP (VIP) is designed to help thoroughly verify PCI Express Gen1, Gen2 and Gen3 designs. With a comprehensive set of protocol, methodology, coverage, verification and productivity features, users can achieve rapid verification closure of their PCIe designs.

PCIe VIP includes software/firmware equivalent application layers that vastly simplify testbench development. These provide
easy-to-use APIs for generating PCIe traffic: a driver application to generate all PCIe transactions, a target application to automatically respond to completion requests and a requester application to generate background traffic. An NVMe Application Layer is also available.

The PCIe VIP is integrated with the Protocol Analyzer, a protocol-aware debug environment that simplifies debug of complex hierarchical protocols like PCIe. PCIe VIP supports UVM and Verilog testbenches and runs on all popular simulators.

Interested in PCIe Gen4 – contact us.

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Discovery VIP for PCI Express

Primary Features
  • Root complex and endpoint models
  • PIPE, PCS/PMA level, or SERDES interfaces
  • Support for Gen 1, 2 and 3, including spread spectrum clocking
  • Includes separate built-in host and target memories
  • Full-link speed and width negotiation up to 32 lanes
  • Automated error injection at all layers (injection, verification and recovery)
  • Scalable architecture supports multiple instantiations to test multi-port hosts or devices
  • Checkers to verify protocol timing checks and functional accuracy at each layer
  • Configurable pattern generation for random, directed or erroneous patterns
  • Status tracking at each level to help determine corner-case coverage
  • User call-backs and hooks for use in directed tests
  • Supports all major simulators

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