Verification IP for MIPI DSI 


Synopsys Discovery™ Verification IP (VIP) for MIPI Display Serial Interface (DSI) helps the verification of DSI Host (typically the application or baseband processor side) or DSI Device (typically the peripheral side). MIPI-DSI VIP supports both High Speed (HS) transmission and Escape Mode. In Escape Mode it supports Ultra Low Power State (ULPS), Low Power Data Transmission (LPDT), Trigger messages and Bus Turnaround. It simplifies testbench development by enabling engineers to use a single VIP to verify multiple transmission modes across the full DSI protocol. Synopsys VIP for MIPI DSI is integrated with the Discovery VIP Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, graphical view of complex and highly interleaved traffic. Synopsys VIP for MIPI DSI is written entirely in SystemVerilog to run natively in the simulator for optimum performance. Testbench development is accelerated with the assistance of built-in verification plans, example tests and a scenario library. Built-in coverage points integrate with the verification plans showing progress towards achieving coverage goal.

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Discovery VIP for MIPI DSI

Primary Features
  • Supports DSI standard with specification revision 1.01.00
  • Compliant with D-PHY specification revision 1.00.00
  • Protocol Layer
    • DSI Host, DSI Device
    • Four virtual channels
    • DCS command, generic commands and Video Mode
    • Short and Long Packet structures
    • Multiple High Speed (HS) packets per transmission
    • Video transmission in burst and non-burst modes
    • 16BPP, 18BPP and 24BPP RGB pixel formats in video mode
    • Normal as well as interleaved data streams, ECC generation, Checksum (CRC) generation and checking
    • Error Detection and Reporting
  • Physical Layer
    • D-PHY Serial and Parallel (PPI) Interface
    • One to four PHY data lanes and one clock lane
  • Methodology Support
    • VMM, UVM and Verilog testbenches
    • Extensive callbacks, protocol checks, notifications, messaging, error injection and functional coverage
  • Includes verification plan
  • Supports all major simulators

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