Discovery Verification IP for MIPI DigRF 


Synopsys Discovery™ Verification IP (VIP) for MIPI DigRF helps the verification of the interface between a Baseband IC (BBIC) and a Radio Frequency IC (RFIC) in a single mobile terminal. It provides support for high speed and low speed operations with multiple standby modes and simplifies testbench development by enabling engineers to use a single VIP to verify multiple speeds across the full DigRF protocol. Discovery VIP for MIPI DigRF is integrated with the Discovery VIP Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, graphical view of complex and highly interleaved traffic. Discovery VIP for MIPI DigRF is written entirely in SystemVerilog to run natively in the simulator for optimum performance. Testbench development is accelerated with the assistance of built-in verification plans, example tests and a scenario library. Built-in coverage points integrate with the verification plans showing progress towards achieving coverage goal.

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Discovery VIP for MIPI DigRF

Primary Features
  • Supports MIPI DigRFv4 version 1.1, 1.0 and .64 specifications
  • Compliant with M-PHY version 1.0.
  • Protocol Layer
    • Configurable low speed (LS) mode, high speed (HS1P, HS2P, HS1S, HS2S) modes, and multiple standby modes (SLEEP, STALL, HIBERNATE)
    • Configurable 1/2/3/4 Tx Lane(s), and 1/2/3/4 Rx Lane(s) per sublink
    • Support for data/control logic channels, ICLC messages, nested frames, dummy frames, IDLE symbols, marker symbols (SOF, EOF and EOT)
    • Link test modes: Ping Message and Clock Test mode
    • Programmable parameters like PREPARE length, SYNC pattern length
    • CRC generation, Error Detection and Retransmission (ARQ scheme: NACK)
  • Physical Layer
    • M-PHY Serial and Parallel (RMMI) Interface
    • Serializer (M-TX) or Deserializer (M-RX), 8B10B coding (M-TX) or 8B10B decoding (M-RX)
    • Support for capability, status and configuration attributes
  • Methodology Support
    • VMM and UVM testbench
    • Extensive callbacks, messaging, error injection and functional coverage
  • Includes verification plan
  • Includes sequence collection
  • Supports all major simulators

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