Ethernet Verification IP 

 

Overview
The Discovery™ Verification IP (VIP) for Ethernet provides complete support for a broad range of Ethernet interfaces from 10/100/1000M to 10G with optional 40G and 100G. With a comprehensive set of protocol, methodology, verification and ease-of-use features, users are able to achieve rapid coverage convergence for their Ethernet-based designs. Discovery VIP for Ethernet is integrated with the Discovery Protocol Analyzer, a protocol-aware debug environment that enables users to quickly debug protocols by raising the abstraction level and providing easy navigation through layers of the protocol hierarchy. Discovery VIP for Ethernet is written entirely in SystemVerilog enabling it to run natively in supported simulators for highest performance. Its System Verilog architecture includes native support for UVM and built-in functional coverage.

Download Datasheet

Discovery VIP for Ethernet

Figure 1: Discovery VIP for Ethernet

Primary Features
  • 10/100M, 1G, 10G, 40G, 100G speed support
  • MII, RMII, GMII, RGMII, SGMII, XGMII, XLGMII, CGMII interfaces
  • TBI, XSBI, XFBI, XLSBI, CSBI, XAUI, XLAUI and CAUI interfaces
  • MDIO clause 22 and clause 45 support
  • Data, pause control, VLAN, PPP, PTP 1588, jumbo frames
  • Forward error correction, auto-adaptation and auto-negotiation
  • Wide range of error injection
  • Checkers to verify functional accuracy
  • Built-in functional coverage
  • Skew insertion and lane reversal
  • Dynamic speed switching
  • Supports System Verilog UVM, OVM and Verilog testbench
  • Supports all major simulators



NewsArticlesBlogsSuccess StoriesWhite PapersWebinarsVideos