Discovery Verification IP for MIPI M-PHY 

Synopsys Discovery™ Verification IP (VIP) for MIPI M-PHY is a multilayered VIP for the verification of M-PHY LINK operating in high speed and low speed modes. It includes many new features to accelerate testbench development, simplify debug, improve performance and achieve coverage closure. The Discovery MIPI M-PHY VIP is integrated with the Discovery Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, graphical view of complex and highly interleaved traffic. Discovery VIP for MPHY VIP is written entirely in SystemVerilog to run natively in the simulator for optimum performance. Testbench development is accelerated with the assistance of built-in verification plans, example tests and a sequence collection. Built-in coverage points integrate with the verification plans showing progress towards achieving coverage goals.

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Figure 1

Primary Features
  • Supports MIPI ALLIANCE specification for M-PHY version 2.0 – 4 April 2012
  • M-PHY layer (L 1.0) features are
    • Interfaces
      • SERIAL-SYS and PWM signaling
      • RMMI – controller and PHY
    • HS and LS GEARS
  • Error injection
  • Supports UVM, OVM and SystemVerilog testbenches
  • Built-in coverage
  • Supports Protocol Analyzer
  • Extensive callbacks and messaging
  • Supports all major simulators
  • M-PORT LM layer (L1.5) features are
    • Configurable number of lanes
    • Supports asymmetrical lanes between TxSubLink and RxSubLink
    • Lane alignment at symbol boundary
    • Lane splitting and merging
    • Configurable number of frames
    • FILLER insertion
    • Error injection
    • M-PORT LM layer system monitor
  • CTRL and DATA SAP interface
    • Interface with protocol adaptor layer
    • Independent port/channel for CTRL and DATA SAPs
    • All capability and configuration attributes
    • LS – HS mode change
    • HS - LS mode change
    • Gear change
    • External/internal SYNC support
    • Automatic FILLER insertion
    • User specific INITIAL state to start the simulation (other than DISABLED)
    • Configurable timing attributes
    • Error injection – protocol level exceptions, 8b/10b & reserved symbol error, includes sequence collection, protocol checks
    • Functional coverage, toggle coverage & verification plan

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