Synopsys VC Verification IP (VIP) is architected to address the challenges of verifying today’s highly sophisticated and complex SoC designs. VC VIP is written entirely in SystemVerilog to deliver greater performance, ease-of-use and extensibility to speed and simplify test bench development, verification and debug. The VC VIP portfolio of bus memory and interface VIP includes support for Verdi Protocol Analyzer, a simulator independent protocol aware debug environment that enables users to quickly debug protocol and memory issues and easily share protocol-based simulation results across teams.
VC VIP Portfolio Datasheet
Verdi Protocol Analyzer DatasheetProtocol Analyzer Video
100% SystemVerilog, Native UVM and VMM
VC VIP is implemented entirely in SystemVerilog and architected for native support of UVM and VMM without the need for methodology-level interoperability wrappers or language translations. It provides full visibility into classes, callbacks, and messages and enables true SystemVerilog-based constraints. This streamlining of the VIP structure results in much greater performance and methodology support; it also provides support across all simulators without degrading performance or methodology.
VC VIP includes productivity features to accelerate complex tasks like configuration and debug. It also provides features that address the need for protocol expertise and accelerate time to coverage-closure. It includes built-in test-plans, coverage,sequences and test suites.
Developing an extensive compliance test suite to cover the full-breadth of a protocol and test compliance of an interface IP to the specification is extremely time consuming, requiring deep protocol and methodology expertise. VC VIP includes availability of pre-built UVM test suites to massively reduce the work needed in building a compliance verification environment. The test suites are included with the VIP and delivered as source code enabling users to easily customize or extend the tests for any unique application-specific or corner-case scenarios and to reuse with their SoC verification environments.
Verdi Protocol Analyzer
With today’s complex protocols, debug has become one of the most difficult and time-consuming aspects of functional verification. Verdi Protocol Analyzer, available with the VC VIP portfolio, provides protocol-centric debug and intelligent visibility. The Verdi Protocol Analyzer gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol. It highlights relationships across the protocol hierarchy, visually unraveling the complex behavior of highly interleaved traffic. Errors, warnings and messages are annotated to quickly find problems in the simulation. This capability enables engineers to quickly understand protocol activity, identify bottlenecks and debug unexpected behavior.
VC VIP - Meeting Today’s Verification Challenges
Designing with the latest industry standard interface protocols and memory is driving verification complexity to new heights. If project teams are to meet increasingly aggressive project timescales, new verification technology is a requirement.
Together with other innovative features, VC VIP streamlines the entire verification process, significantly reducing the time and effort required to achieve project schedules and coverage goals.