1. What is Synopsys Announcing?

    Answer: Synopsys is announcing the availability of Discovery VIP, a new product line of Verification IP (VIP) based on a next-generation VIP architecture. Discovery VIP is implemented entirely in SystemVerilog utilizing native UVM, VMM and OVM methodologies.

    Commercial VIP solutions today are based on 10-year-old architectures that result in performance degradation and provide few capabilities for debug, SoC integration and coverage management. As protocols have become more complex and numerous, this has created increasing difficulties in verification. Discovery VIP addresses the shortcomings of other commercial VIP solutions based on older architectures.

  2. What is Verification IP (VIP)?

    Answer: Verification IP (VIP) is pre-written testbench components that enable the verification of the industry standard interface protocols, such as USB, Ethernet, AMBA, etc. used in systems on chips (SoCs) for many commercial electronic products. VIP reduces verification cost and time for SoC verification. VIP needs to act as the opposite side of the interface being tested; for example, a USB Device VIP is needed to verify a USB host design, or the integration of a USB host design into a SoC. VIP typically includes monitors, checkers, coverage, test-plans, example tests and protocol-centric sequences. VIP is available for on-chip buses to verify interconnect and IP interfaces, and off-chip buses to verify interfaces to other components or products.

  3. Why is VIP important to SoC verification teams?

    Answer: VIP enables the early verification of design RTL to validate that the system interfaces conform to industry-standard specifications and consequently, that electronic products will be able to communicate with other products as needed to meet their end-user requirements. As interfaces have grown massively in performance and complexity, the internal development of testbench components to rigorously test them has become a daunting task, requiring deep expertise in the protocol and many months of coding and testing. Reusable commercial VIP enables customers to focus their verification effort on verifying the design instead of creating, validating and supporting VIP; it also gives them a robust protocol model that has been used widely and proven across many designs. Verification IP shaves months of effort from a verification project and instills confidence that the interfaces are working as expected.

  4. What are the main issues with VIP today?

    Answer: Commercial VIP solutions today are based on 10-year-old architectures that make use of wrappers that translate the current testbench languages and methodologies into underlying protocol models implemented in a different language like C, ‘e’, or OpenVera. With the standardization of SystemVerilog and introduction of verification methodologies such as UVM, VMM and OVM, the VIP has been wrapped (“gasket-ed”) and patched to make it work in these advanced testbenches. With these wrappers and patches, commercial VIP, while still able to do the job, has become sluggish, hard to integrate, difficult to use and time-consuming to debug. With current VIP in the market, it is not uncommon for 2-4 weeks to pass before the VIP is integrated into a test environment and the verification team can start testing. It can take upwards of 3 man-months to implement coverage and scenarios in a test environment. It is also not uncommon to see several days wasted finding the root cause(s) of common protocol errors using the basic methods of log files, transcripts and trace data. Little if any help is provided in identifying bottlenecks.

  5. How is Discovery VIP different from other VIP today?

    Answer: Discovery VIP is implemented in a completely new VIP architecture (named VIPER). This next- generation VIP architecture is designed from the ground-up to address the challenges faced with today’s commercial VIP: performance, methodology support, long set-up-times to start first test (configuration and SoC integration), ease of use, protocol debug and coverage management. Based on this architecture, each Discovery VIP is written entirely in SystemVerilog with UVM, VMM and OVM base classes built natively into the VIP (i.e. no wrappers and gaskets are used).

  6. What are the key features and benefits of Discovery VIP?


    • High performance (up to 4X faster than other commercial VIP today)
    • 100% SystemVerilog; native UVM, VMM and OVM
    • Protocol-aware debug: Protocol Analyzer, a graphic protocol-centric debug environment
    • Configuration Creator: Automates configuration of complex protocol interfaces, eases SoC integration of VIP in test environment
    • Built-in coverage, test plan, scenarios
    • Supports all simulators

  7. What is included in Discovery VIP?


    • Protocol testbench (VIP)
    • Protocol Analyzer (with Intelligent Visibility)
    • Configuration Creator
    • QuickStart (Wizard-like HTML documentation on VIP integration)
    • Built-in coverage and test plan (directly mapping to protocol specification document)
    • Protocol-centric sequence library
    • Test suites

  8. What is Protocol Analyzer?

    Answer: Protocol Analyzer is a unique protocol-aware debug environment, introduced and available with Discovery VIP. With increasingly complex protocols, debug has become one of the most difficult and time-consuming aspects of functional verification. Protocol Analyzer is a GUI-based environment with unique protocol-centric debug technology and intelligent visibility into VIP source code. This capability enables engineers to quickly understand protocol activity, identify bottlenecks and debug unexpected behavior.

  9. What is intelligent Visibility?

    Answer: Intelligent Visibility is a debug feature that provides verification engineers a source-code view of the encrypted VIP. It enables them to trace the VIP internal states and variables during simulation and set breakpoints in the internal states of the VIP to assist in stepping through the simulation process.

  10. Does Discovery VIP support third-party simulators?

    Answer: Since Discovery VIP is written 100% in SystemVerilog, it inherently supports all major third-party simulators. Furthermore, each Discovery VIP is tested via large regression suites at Synopsys to ensure full compatibility with Synopsys VCS, Cadence Incisive and Mentor Questa simulation environments.

  11. How do I get more information about Discovery VIP?

    Answer: For more information, please visit the Synopsys VIP website: www.synopsys.com/vip.

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