HDMI Verification IP 

The Discovery™ Verification IP (VIP) for HDMI is for the verification of HDMI Source and Sink Devices with support of EDID, CEC and HDCP. It supports changing of video and audio related configurations during simulation and also enables easy addition of new video formats. The Discovery VIP for HDMI is integrated with the Synopsys VIP Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, graphical view of complex and highly interleaved traffic. The Discovery VIP for HDMI is written entirely in SystemVerilog to run natively in the simulator for optimum performance. Testbench development is accelerated with the assistance of built-in verification plans, example tests and a scenario library. Built-in coverage points integrate with the verification plans showing progress towards achieving coverage goal.

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Figure 1

Primary Features
  • Supports HDMI 1.3a, 1.4a, 1.4b
  • Display Data Channel (DDC/EDID)
  • Character Synchronization by Sink
  • All Deep Color Support
  • AvMute Support
  • xvYCC Support
  • DVI (Single Link) Compatibility
  • CEA-861-E Video formats (1 to 64)
  • All 4kx2k and all 3D Video formats
  • New YCC Video Quantization Ranges
  • Pixel Repetition
  • All Pixel Encoding formats
  • Video Pixel Rates
    • Pixel Rates between 25Mhz to 165Mhz
    • Pixel Rates below 25Mhz (Pixel Repetition Scheme Support is needed)
  • Content types like Graphics, Cinema, Photo, Game
  • Low Frequency Effect (LFE)
  • Methodology Support
    • VMM, UVM, OVM and Verilog testbenches
    • Extensive callbacks, messaging, error injection and functional coverage
  • CEC Protocol, HDCP Protocol, Data Island Period feature support
  • Includes verification plan
  • Supports all major simulators

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