Discovery Verification IP for AMBA 4 AXI 

Synopsys® Discovery Verification IP (VIP) for ARM® AMBA® 4 AXI™ provides complete protocol support for AXI3™, AXI4™, AXI4-Lite™, AXI4-Stream™, ACE™, ACE-Lite™ interfaces, AHB™ and APB™. With a comprehensive set of protocol, methodology, verification and productivity features, users are able to achieve rapid verification convergence on their AMBA-based designs. Discovery VIP for AMBA 4 AXI is integrated with the Discovery Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, graphical view of complex and highly interleaved traffic. Discovery VIP for AMBA 4 AXI is written entirely in SystemVerilog to run natively in the simulator for optimum performance. Testbench development is accelerated with the assistance of built-in verification plans, example tests and sequence library. Built-in coverage points integrate with the verification plans showing progress towards achieving coverage goal.

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Figure 1

Primary Features
  • Complete protocol support for
    • AXI3, AXI4, AXI4-Lite, AXI4-Stream, ACE, ACE-Lite, AHB and APB
  • System and port level protocol checks for AXI3/4/Lite, AXI4-Stream and ACE/ACE-Lite, AHB and APB protocols
  • Built-in functional coverage and verification plans
  • Built-in UVM sequence library
  • Performance checking – latency and throughput
  • Ability to control delays for valid and ready signals with respect to reference events
  • Ability to control signal values during idle periods
  • Configurable interconnect model
  • Backdoor access to ACE master cache
  • Includes configuration tool
  • Graphical view using Protocol Analyzer for easy debug
  • Debug port for transaction tracking on waveform
  • Methodology Support
    • VMM, UVM, OVM and Verilog testbenches
    • Extensive callbacks, messaging and functional coverage
  • HTML reference docs, methodology specific user guides
  • Includes Reference Verification Platform
  • Supports all major simulators

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