20X Power Analysis Performance Improvement with Synopsys Verdi Technologies
Discover how Synopsys' Verdi technologies, Siloti Correlation and Siloti What-If Replay Simulation, can enable up to 20X performance improvement for power analysis – from weeks to hours. These technologies enable the use of RTL simulation results to generate gate-level simulation data without the need to bring up the gate-level environment, thus enabling power analysis at early stages of the design cycle. Also included is parallel run technology to enhance performance up to 60X compared to the original flow.
Rich Chang, Product Marketing Manager, Debug, Synopsys
Sep 16, 2015
Learn How to Accelerate Verification Closure with PCIe Gen4 VIP
This webinar shows how to leverage protocol, methodology, verification and productivity features of Synopsys VC VIP and UVM source code test suites for accelerated verification closure of PCIe Gen4 based designs.
Paul Graykowski, Senior Manager, PCIe VIP, Synopsys
Aug 19, 2015
Addressing Verification Challenges of Evolving Ethernet Speeds from 25/40/50/100G and Beyond
We will outline in detail the verification challenges of current and future Ethernet speeds and explain how Accellera UVM Methodology, IEEE 1800-2012 System Verilog Functional Coverage, and SystemVerilog Ethernet Verification IP empowers design and verification teams with methodology, techniques and tools they need to achieve success.
Shenoy Mathew, Senior Corporate Applications Engineer, Verification Group, Synopsys
May 20, 2015
Picking up the pieces: self-contained verification platforms for the modular smartphone era
In the framework of Mobile platforms, learn how source code testsuites provided with Verification IP enable verification engineers to quickly generate diverse permutations of random/constrained random transactions that stress test the systems and subsystems, contributing to "Shift Left" of the verification time and ensure bug free designs.
Nitin Agrawal, CAE Manager, Verification Group, Synopsys
Apr 07, 2015
Avoiding the Common Pitfalls of ARM-based Cache-coherent Verification and Performance Analysis
Synopsys will cover how verification IP for AMBA enables users to generate correct and interesting coherent stimulus for cache coherent SoC verification. This will include the complexities of configuration, stimulus, coverage and checking, as well as how to address the common verification pitfalls.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Tushar Mattu, Corporate Application Engineer (CAE) for Verification Group, Synopsys
Dec 03, 2014
The 10 Things to Know About Memory Verification: Synopsys Memory VIP
Learn how feature-rich, native SystemVerilog memory VIP rapidly verifies the memory interfaces on complex designs, focusing on 10 key areas where productivity is improved.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Nasib Naser, PhD, Senior Staff Corporate Applications Engineer, Synopsys
Oct 23, 2014
Reinventing Coverage and Planning with Verdi—A Fully Integrated, Complete Verification Closure Flow To Help You Deliver Chips On Time
The Synopsys Verdi® Coverage solution provides comprehensive planning and coverage analysis technologies as a part of the industry-leading Verdi3™Automated Debug System. We'll discuss why Synopsys' native integration of planning, coverage, and debug technologies provide a complete closure solution to help meet demanding schedules and provide teams with more confidence when asked the inevitable question: '"Are we done yet?"
Steve Chappell, Senior Product Marketing Manager, Debug and Analysis, Synopsys; Michael Horn, Verification Technologist, Synopsys
Oct 14, 2014
Addressing IP Compliance Challenges with UVM-based Test Suites
Protocol verification is a massive time- and resource-consuming endeavor, fraught with complexity and the risk of errors and omissions. Synopsys Verification Test Suites leverage the expertise of protocol experts to provide a rapidly deployable and extensible set of comprehensive tests, written in easily modifiable and reusable SystemVerilog UVM source code. The webinar will give an overview of the architecture and scope of Synopsys’ Verification Test Suites to achieve faster and higher quality coverage closure.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Karim Aoua, Staff CAE, Synopsys
Sep 30, 2014
Advanced Mixed-Signal Design and Verification of Smartcar ICs
In this webinar, Micronas and Synopsys discuss the breadth of automotive IC applications, challenges in design implementation and verification and the solutions that stemmed from their collaboration.
Mario Anton, Micronas; Gernot Koch, Micronas; Marco Casale-Rossi, Synopsys
Jul 31, 2014
Extending Proven Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS
VCS AMS provides mixed-signal verification with a unique performance advantage due to tight integration of VCS functional verification and CustomSim FastSPICE simulation. Webinar topics include an introduction of the new VCS AMS mixed-signal verification solution, RNM with VCS, the SystemVerilog-based AMS testbench methodology, low power verification using UPF power intent specification and AMS debug with Verdi.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; Arturo Salz, Synopsys Scientist, Verification Group, Synopsys
May 21, 2014
VCS Xprop: Catch X-Related Issues at RTL to Reduce Time-Consuming Gate-Level Simulations
In this webinar you'll learn about a new technology in VCS, called Xprop, which eliminates 'x' optimism at RTL to enable correlation with hardware design behavior. Xprop can be used to reduce and potentially eliminate gate-level simulations for 'x' validation. This webinar will also show how VCS® Xprop eliminates 'x' optimism in advanced simulation flows (such as VCS-NLP) and demonstrate how to debug 'x'-related issues identified by VCS-NLP and Xprop using Verdi™ Power-Aware Debug.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys
Nov 05, 2013
How VCS Improves Coverage Driven Verification Efficiency with Integrated Planning and Management
VCS provides a scalable and integrated planning, management and analysis solution for metric-driven verification. In this webinar, you'll learn how to track coverage and test data in order to correlate results with project goals and resources, so teams know where they are in the verification process and how they have allocated resources. These features are available in VCS 2013.06.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; Bart Thielges, R&D, Verification Group, Synopsys
Sep 17, 2013
Improve Stimulus Quality and Verification Completeness with VCS Constraint Debug
In this webinar, you will learn about new constraint debug features available in VCS 2013.06. In the batch mode, we will show you how to debug solver solutions as well as improve solver performance. In the interactive mode, we will show you how to stop the simulation on randomize calls, explore the solution and relation spaces in the randomize call, examine the solution distribution of random variables, and modify constraints, re-compiling the design interactively for effective what-if analysis.
Rebecca Lipon, Senior Product Marketing Manager, Synopsys; Jason Chen, CAE, Synopsys; Dhiraj Goswami, Scientist, R&D, Synopsys
Jun 25, 2013
Verilog-to-Verilog Equivalence Checking Using ESP
This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed.
Philip Schmidt, R&D Manager, Synopsys; Dave Hedges, Corporate Applications Engineer, Synopsys
May 29, 2013
Accelerate PCIe Integration Testing with Next-Generation Discovery VIP
Learn an optimal strategy for integration testing using UVM in conjunction with next-generation features of PCIe VIP for more efficient test development, error injection and debug.
Neill Mullinger, Product Marketing Manager, Synopsys; Paul Graykowski, Corporate Application Engineer (CAE), Synopsys
Mar 20, 2013
Functional Signoff: Measuring and Improving Verification Quality to Ensure Bug-Free Designs
In this webinar you will learn how Certitude Functional Qualification can be added to traditional coverage techniques, to provide unique insight into the quality of RTL simulation and formal verification environments. Certitude uses a proprietary mutation-based process to insert “artificial bugs” or faults into the design and measure the ability of your existing verification environment to detect these faults. The results of this process provide an objective measure of overall verification quality – the ability of the environment to activate, propagate and detect potential bugs – and identify specific holes and weaknesses like incomplete test scenarios, missing checkers and assertions, or infrastructure problems that can allow RTL bugs to slip through the process undetected. Fixing these weaknesses makes your verification environment stronger and reduces the risk of signing off or taping out with functional bugs.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; George Bakewell, CAE Director, Verification Group, Synopsys
Jan 10, 2013
Using Advanced Verification IP Capabilities to Accelerate Ethernet Verification
This webinar will be based around a typical Ethernet switch design including a processor, switch fabric and Ethernet MACs. Learn how SystemVerilog, UVM and VIP are utilized to verify the Ethernet digital core and then integration of the core into the system. We also cover advanced VIP features, including test suite and debug, to accelerate productivity.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Jaspreet Singh Gambhir, R&D Manager for Verification IP, Synopsys
Dec 11, 2012
Deploying UVM Effectively: How to Simplify Testbench Debug and Improve Turn-around-time with VCS
Learn how to utilize VCS and DVE to most effectively deploy, debug and optimize UVM testbenches.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; Adiel Khan, Corporate Applications Engineer (CAE), Verification Group, Synopsys
Oct 02, 2012
Verification of MIPI Protocols on a Mobile Platform SoC
This webinar is based around a MIPI-based mobile platform that consists of an application processor, baseband IC and RF IC with interfaces to the peripheral devices like camera, and display. The Webinar shows how SystemVerilog, UVM and verification IP (VIP) are utilized to verify the SoC that implements that platform. It will specifically focus on how to validate the data flow for typical scenarios involving the camera (CSI) and display (DSI) interfaces.
Neill Mullinger, Product Marketing Manager for Verification IP, Synopsys; Narasimhababu GVL, Senior R&D Manager for Verification IP, Synopsys
Aug 07, 2012
Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ VIP
Overview of challenges of verifying a coherent design. Shows how the features and architecture of Synopsys’ new Discovery VIP helps overcome these challenges to simplify verification of ACE design.
Abhijeet Khopkar, R&D Manager, Synopsys; Neill Mullinger, Group Marketing Manager, Synopsys
May 08, 2012

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