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Broadcom addresses tough verification challenges with VCS
YC Wong, Director of IC Engineering, explains how close technical collaboration between Broadcom and Synopsys helped with faster, better verification

Dynamics of consumer market requires short development cycle for design as well as verification. Furthermore, complex convergence SoC (Cellular, WLAN, Bluetooth, GPS, FM, etc.) demands make verification even more challenging with performance requirements that require lots of computing resources. In this video, YC Wong of Broadcom discusses how close technical collaboration with Synopsys helped with faster, better verification, and how VMM was a key technology to increase verification productivity.

Click Play – then select the chapter labeled Broadcom - Touch Verification Challenges in Consumer IC Market - YC Wong.


Sun Microsystems verifies multi-threading processors using VCS
Shrenik Mehta, Senior Director of Frontend Tools and OpenSPARC, describes the use of VCS Multicore technology to keep pace with increasing demand on verification performance and technology

Sun Microsystems has complex verification needs that include verification of processor cores and SoC components (memory, I/O and networking) in both architectural and implementation domains, as well as verification of the software stack. At the same time, they need scalable simulation performance for assertions, testbench, coverage, and debug. In this video, Shrenik Mehta of Sun Microsystems illustrates achieving verification of large full chip random cycles without a hardware failure due to VCS’ scalable performance and full chip capacity.

Click Play – then select the chapter labeled Sun Microsystems - Verification of Chip Multi Threading (CMT) Processors Using VCS - Shrenik Mehta.


Qualcomm builds a verification methodology based on VMM
Faisal Haque, Director of Engineering, illustrates an effective way to reduce the ramp up time significantly

SoC complexity is growing exponentially especially when including power-aware functionality in the SoC’s. At the same time, there’s elevated expectation for faster time to quality and higher quality. In order to meet these challenges, a globally scalable methodology is needed to increase productivity of verification engineers. In this video, Faisal Haque of Qualcomm discusses creation of a simple yet productive methodology based on VMM targeted for design engineers enabling them to reduce the verification ramp up time.

Click Play – then select the chapter labeled Qualcomm - A Simple Verification Methodology based on VMM - Faisal Haque.


AMD verifies digital blocks, arrays, and mixed-signal cores using VCS
Amit Chowdhry, Member of Technical Staff, depicts enablement of functional verification of mixed signal IPs

Verification of a multi-domain SoC requires the ability to handle several design paradigms including pure digital blocks, mixed-signal blocks, and analog blocks such as PLLs, DLLs, and PHYs. In addition, these SoC’s frequently include several voltage planes. In this video, Amit Chowdhry shares details of AMD’s use of VCS for verification of multiple generations of multi-domain SoC’s.

Click Play – then select the chapter labeled AMD - Array Mixed Signal IP Verification Overview - Amit Chowdhry.