Verification Compiler  

Comprehensive, Best-in-Class, Natively-Integrated Functional Verification Platform 

The Verification Compiler™ Platform is Synopsys’ natively integrated next-generation solution for functional verification of advanced SoC designs. The Verification Compiler Platform provides:

  • Comprehensive support for all Synopsys simulation flows, including Native Low Power, X-propagation, planning, coverage and execution management
  • Support for Synopsys’ industry leading SoC debug flows, including Power-Aware, HW/SW, and reverse interactive debug
  • Compelling native integration features, providing up to 2-3X performance improvement and 3X productivity improvement, between all of Synopsys’ VC VIP titles and the Synopsys simulation and debug flows

Verification Compiler Datasheet

Key Benefits

Next-generation technologies
  • Advanced formal verification
  • UVM-based, SystemVerilog VIP
  • High performance, high capacity simulation with natively-integrated X-propagation and Native Low Power
  • Verification planning, coverage, and management
  • Advanced multi-domain debug
2-3X performance increase with native integrations
  • Unified compile across simulation, debug and formal
  • Complete power-aware verification with integrated Native Low Power simulation and power-aware debug
  • Native testbench quality analyzer in simulation with Certitude® technology
  • Natively integrated simulation-debug flow enabling 3X faster dumping and 3X smaller database size

Figure 1: Verification Compiler Platform
Figure 1: Verification Compiler Platform

Key Technologies

Next-generation formal verification
  • Next-generation model and property checking (Figure 3)
  • Formal SoC connectivity checking
  • C-to-RTL transaction equivalency checking
  • RTL-to-RTL sequential equivalency checking
  • Advanced SoC debug based on the industry-leading Verdi™ debug environment
  • Power-aware, HW/SW, advanced mixed-signal (AMS) and interactive debug (Figure 2)
  • Transaction-level debug and protocol analyzer
  • Advanced coverage plan management, analysis and exclusion manager
  • Extensible with VC apps
  • Highest performance and capacity simulation capability available
  • Most widely trusted and deployed simulation solution in the industry
  • Native Low Power
  • X-propagation
  • Comprehensive and growing title availability
  • Next-generation SystemVerilog architecture titles
  • Test suites
  • RTL, gate-level and C/C++ fault injection
  • Advanced coverage analysis, planning and execution management
  • Full coverage capabilities natively integrated in Verdi environment

Figure 2. Interactive testbench debug
Figure 2: Interactive testbench debug

Key Integrations

Simulation and debug integration
  • Unified compile: consistent compile behavior, 35% lower compile overhead and 2X faster debug-mode simulation
  • Native Siloti®, incremental KDB, coverage analysis with Verdi®, AMS integration
Simulation formal/coverage integrations
  • Unified compilation across engines for consistent support and reduced compilation overhead
  • Formal coverage convergence: unified setup, coverage database and reporting
  • Automated unreachability analysis and exclusion management
  • Native Certitude: simplified single step use model, same language set support, seamless support for all simulation technologies and optimal runtime performance
  • Execution Manager support for formal and Certitude, fault propagation using multi-fault simulation
Simulation and VIP integrations
  • High-performance VIP models: optimized constraints and code for best simulation performance, and optimized debug capabilities
  • Built-in support for simulation technologies: precompiled IP, verification plan and coverage closure
  • Built-in Execution Manager support and coverage convergence
Formal, VIP and coverage integrations
  • Formal engine integration with Certitude

Figure 3. Next-generation formal verification
Figure 3: Next-generation formal verification

Figure 4. Verification Compiler Platform’s next-generation technologies
Figure 4: Verification Compiler Platform’s next-generation technologies

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