Functional Verification 

Industry-leading High-performance RTL Verification Accelerates Innovation 

Increases in the size and complexity of today’s SoCs have intensified the challenges of verification. Meeting these challenges requires advanced technologies and methodologies that ensure the highest design quality. The Synopsys suite of functional verification solutions are tightly integrated, best-in-class technologies that allow designers to find bugs quickly and easily, significantly improving the quality of the most complex designs and enabling first-pass silicon success. These tools include VCS, the functional verification solution used by leading SoC teams; VCS Xprop for X-propagation support for X-related simulation and debug; Verdi, the Industry’s de facto debug platform for design and verification; ZeBu, the industry’s performance and capacity leader in emulation; Discovery Verification IP, the industry’s next-generation VIP; MVSIM and MVRC for multi-voltage native low-power simulation and low-power rule checking; Certitude, for overall verification suite quality measurement and debug; Magellan, the formal hybrid verification solution; Leda, the static checking solution; and HECTOR, the next-generation formal block-level consistency checker..

 

  • VCS
  • High-performance simulation more

 
High-performance simulation

  • VCS Xprop
  • X-propagation support for X-related simulation and debug more

 
X-propagation support for X-related simulation and debug


 
VIP that simplifies testbench development, provides better coverage and delivers significant improvements in simulation runtime performance


 
An intelligent voltage-aware simulation engine that understands the waveform nature of voltage and covers all power states, transitions and sequences
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A true voltage-aware static checker that enables rapid power management verification
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Functional qualification system


 
Billion Gate, Multi-user ASIC and SoC Emulation


 
High capacity, superior performance and the ability to program and check for complex hardware rules enables the early detection of design bugs


 
The strengths of advanced formal engines combined with the power of a built-in VCS simulation engine to verify properties on large, complex designs


 
High-performance testbench automation that delivers up to 2X faster verification runtime performance

  • HECTOR
  • Next-generation formal block-level consistency checker more

 
Delivers high-performance checks between independently developed models and exhaustive verification of successive design refinements all without testbenches, assertions or coverage.

  • High-performance and high-capacity simulation, advanced testbench automation, assertion verification, coverage analysis and SystemVerilog support in a single product
  • Most effective solution to find more bugs in less time
  • Based on industry standards to secure your verification investments


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