DAC 2014 Verification Lunch Panel 


DAC 2014 Verification Lunch Panel: SoC Leaders Verify with Synopsys

On June 3, 2014, Synopsys hosted a luncheon event at DAC in San Francisco, CA. At this event, Dave DeMaria, VP of marketing and business development at Synopsys highlighted next-generation verification technologies including Verification Compiler, advanced static and formal technology, and the industry's fastest emulation system ZeBu Server-3, as well as discussions about the latest developments in the verification landscape and advanced technology trends. A panel of industry experts from AMD, Analog Devices, Cisco, Freescale, and Imagination discuss their insights on SoC verification challenges and how they collaborate with Synopsys to address them.


Dave DeMariaNext-Generation Verification Technologies
Dave DeMaria, Vice President of Marketing
Venkataraman SrinivasagamClock Domain Crossing Static Verification Challenges of Next Generation ASICs
Venkataraman Srinivasagam, Technical Leader
Todd HonanAddressing Verification Challenges at Analog Devices
Todd Honan, Design Verification Manager
Analog Devices
Alex StarrRethinking AMD's Cost of Verification
Alex Starr, Fellow & Pre-Silicon Solutions Architect
Amol BhingeAccelerating SoC Verification Turn Around Time
Amol Bhinge, Senior SoC Verification Manager
Colin McKellarEnabling Faster Verification of Imagination IPs
Colin McKellar, Senior Director of HW Verification

Panel ListSpeaker

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