This DAC 2008 event provided an opportunity for verification engineers to hear a panel of industry verification experts explore the current state of the art in verification methodologies and discuss how methodology is expanding beyond simple base class libraries to address important issues such as verification of low-power designs, modeling and verification of on-chip register structures and disciplined approaches to verification planning.
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ARM, Ltd.
Need for a Low Power Verification Methodology
Alan Hunter, Verification Methodology Lead
Learn about ARM and Synopsys’ joint efforts to develop a Verification Methodology for Low Power Designs.
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Renesas Technology Corporation
Low Power Verification User Experience
Yoshio Inoue, Chief Engineer
See a presentation on the unique challenges of low power design verification and how they are being addressed by Reneses using Synopsys' tools.
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NVIDIA
Engineering the APX2500: Verification Methodology for Low Power
Soma Bhattacharjee, Director of Engineering
Watch a presentation on NVIDIA’s experience using the Verification Methodology for Low Power Design on the APX2500, the world’s lowest power, high definition video and graphics computer on a chip.
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IBM
"Are We There Yet?"
Nancy Pratt, BIST Verification Lead
Listen to a discussion on VMM Planner and how IBM used it on their BIST project to determine when they had run enough random tests.
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