|Feb 03, 2015||Synopsys’ New 25G/50G Ethernet Verification IP Enables Next-Generation Gigabit Designs|
Native SystemVerilog Ethernet VIP and Source Code Test Suites Enhanced with Built-in-Coverage and Support for Protocol-aware Debug
|Dec 09, 2014||Synopsys' New LPDDR4 Verification IP Accelerates Verification Closure for High-Performance Low Power Designs|
Native SystemVerilog-based Memory VIP Portfolio Expanded to Support JEDEC LPDDR4 with Built-in Coverage, Verification Plan and Protocol-aware Debug
|Nov 11, 2014||Nitero Achieves First-Pass Silicon Success for Industry's First Mobile 60GHz SoC Using Synopsys DesignWare IP for PCI Express and Tools|
High-Quality DesignWare IP, Verification IP and Galaxy Design Platform Tools Deliver Lower Power, Smaller Area and Faster Time-to-Market for Wi-Fi Networking SoC
|Oct 27, 2014||SK Hynix Accelerates Memory Development with Productivity-Enhancing Debug Apps on Synopsys Verdi|
VC Apps open APIs automate memory testbench generation and debug. SK Hynix, Inc. has addressed their debug challenges by adopting the Synopsys VC Apps open application programming interfaces (APIs) to directly link their internally developed test generation technology to the industry-leading Synopsys Verdi® debug solution and allow their design and verification teams to customize their debug experience and boost debug productivity.
|Oct 14, 2014||Synopsys Enables Superior Verification Planning and Coverage Analysis with Verdi Coverage|
Verdi Coverage enables users to understand project progress, manage regression data, launch verification jobs, track project trends, generate reports and ultimately optimize resource allocation. This solution addresses the growing challenge of verification closure for complex system-on-chips (SoCs) by introducing advanced technology that allows users to quickly create efficient verification plans, integrate third-party and user-defined metrics, link plans to requirement documents, and intuitively track project and test-level metrics across simulation, static checking, formal verification, VIP and FPGA-based prototyping.
|Oct 07, 2014||Synopsys Releases Verification IP for Mobile PCIe Technology|
Native SystemVerilog-based VIP for PCI Express architecture now supports M-PCIe technology, with built-in coverage, verification plan and protocol-aware debug
|Sep 23, 2014||Synopsys Unveils Verification Continuum to Enable Next Wave of Industry Innovation in Software Bring-Up for Complex SoCs|
Next-generation verification platform to accelerate time-to-market by months. The Synopsys Verification Continuum platform accelerates industry innovation for earlier software bring-up and shorter time-to-market for advanced SoCs. Verification Continuum is built from Synopsys' market-leading and fastest verification technologies providing virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping and debug in a unified environment with verification IP, planning and coverage technology.
|Sep 17, 2014||Synopsys' New MIPI C-PHY Verification IP Accelerates Adoption of MIPI Alliance's Physical Layer Specifications|
Native SystemVerilog-based MIPI C-PHY Verification IP Broadens Synopsys' VIP Portfolio Enabling Verification of Full Family of MIPI Alliance PHY Options
|Sep 17, 2014||Synopsys' New DesignWare MIPI D-PHY Cuts Area and Power by 50 Percent|
Industry-First Support for MIPI D-PHY v1.2 Specification Increases Performance to 2.5 Gbps While Lowering Cost for Image Sensor and Display Applications
|Sep 10, 2014||Wipro Accelerates SoC Verification with Synopsys Verification IP Portfolio|
Native SystemVerilog-based VIP Used in Advanced Testbench Methodology Environment to Address SoC Verification Challenges
|Jul 15, 2014||Emulex Accelerates Verification Closure with Synopsys Verification IP for Ethernet|
Native SystemVerilog Ethernet 1G/10G/40G/100G VIP now includes UNH compliance source-code test suite
|Jul 08, 2014||Synopsys Expands Verification IP Portfolio with Compliance Test Suites|
Protocol test suites in SystemVerilog source code accelerate compliance testing of Ethernet, USB, PCI Express, ARM AMBA AXI and MIPI CSI-2 protocols
|Jun 03, 2014||Synopsys Expands Verification IP Portfolio with Memory Models|
DDR and LPDDR Verification IP Now Broadly Available
|May 28, 2014||Synopsys Bridges Design and Verification with Next-Generation Static and Formal Technology for Verification Compiler|
Synopsys announces the availability of its VC Formal comprehensive formal verification solution, and VC CDC and VC LP advanced static checking solutions. These solutions address the growing verification challenges of complex SoCs by introducing next-generation verification technology that finds bugs earlier, faster and more accurately, as well as accelerates root-cause analysis.
|May 22, 2014||Synopsys Unveils Industry's First Complete PCI Express 4.0 IP Solution|
High-Quality DesignWare PHY, Controller and Verification IP for PCI Express Architecture Doubles Performance to 16 GT/s for Enterprise SoC Designs
|Apr 23, 2014||Synopsys Announces Industry's First Complete LPDDR4 IP Solution for High-Performance, Low-Power Mobile SoC Designs|
PHY, Controller and Verification IP Deliver up to 3200 Mbps Speeds for High-End Smartphones and Tablets
|Mar 25, 2014||Synopsys Unveils Advanced Mixed-Signal Verification Initiative to Accelerate Regression Testing of Mixed-Signal SoCs|
Initial Components of Initiative Extend Proven Verification Methodology and Technologies for Mixed-Signal Applications
|Mar 04, 2014||Synopsys Introduces Verification Compiler to Enable 3X Productivity|
Synopsys Introduces Verification Compiler to enable 3X productivity and deliver next-generation software technologies for complete verification flow. Verification Compiler is a complete portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure to create a complete functional verification flow with a single product.
|Feb 25, 2014||Synopsys Delivers Industry’s Fastest Emulation System|
ZeBu Server-3 speeds hardware-software bring-up, OS boot and SoC verification by up to 4X for faster time-to-market on even the largest designs
|Feb 25, 2014||Imagination Technologies and Synopsys Collaborate to Enable Faster Emulation|
ZeBu Server-3 emulator achieves 3.5 MHz performance on PowerVR Series 6 GPU to speed driver development and SoC verification
|Jan 21, 2014||Synopsys Expands Memory Verification IP Portfolio with UFS, UniPro and eMMC to Accelerate Verification Closure for Mobile Designs|
Synopsys memory VIP is based on a native SystemVerilog architecture to enable enhanced ease of use, integration and configurability.
|Mar 19, 2013||Micronas Standardizes on Synopsys’ Design and Verification Solutions for Automotive Designs|
Solutions Include Galaxy Custom and Digital Implementation, Discovery Verification Platform
|Jan 30, 2013||Imagination Technologies Selects Synopsys as Advanced Verification Technology Partner|
Multi-year Collaboration Results in Deployment of Synopsys' Advanced Formal Debug Technology for Verification of PowerVR Graphics Intellectual Property (IP) Cores
|Jan 21, 2013||Freescale Boosts Verification Productivity with Synopsys Verification IP|
Companies extend system-on-chip (SoC) verification collaboration on simulation, debug and verification IP. Synopsys today announced advancements in its longstanding verification collaboration with Freescale® Semiconductor. With a focus on addressing the increasing complexities of SoC verification, Freescale teams are leveraging Synopsys' innovations in next-generation verification IP (VIP), simulation performance, debug technology and methodology development. This collaboration is targeted to achieve better schedule predictability and lower overall verification costs for Freescale's complex SoCs.